參數(shù)資料
型號： CS4265-DNZR
廠商： Cirrus Logic Inc
文件頁數(shù)： 20/46頁
文件大小： 0K
描述： IC CODEC 24BIT 104DB 32-QFN
標準包裝： 6,000
類型： 立體聲音頻
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
動態(tài)范圍，標準 ADC / DAC (db)： 104 / 104
電壓 - 電源，模擬： 3.13 V ~ 5.25 V
電壓 - 電源，數(shù)字： 3.13 V ~ 5.25 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 32-QFN
供應商設備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 598-1001-ND - BOARD EVAL FOR CS4265 CODEC
DS657F3
27
CS4265
4.4
Analog Input Multiplexer, PGA, and Mic Gain
The CS4265 contains a stereo 2-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer is able to select either a line-level input source, or a mic-level input source, and
route it to the PGA. The mic-level input passes through a +32 dB gain stage prior to the input multiplexer,
allowing it to be used for microphone-level signals without the need for any external gain. The PGA stage
provides 12 dB of gain or attenuation in 0.5 dB steps. Figure 11 shows the architecture of the input multi-
plexer, PGA, and mic gain stages.
The “Analog Input Selection (Bit 0)” on page 41 outlines the bit settings necessary to control the input mul-
Address 08h” on page 40 outline the register settings necessary to control the PGA. By default, the line-
level input is selected by the input multiplexer, and the PGA is set to 0 dB.
4.5
Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject sig-
nals within the stopband of the filter. However, there is no rejection for input signals
which are
(n 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capac-
itors which have a lar ge voltage coefficient (such as ge neral-purpose ceramics) must be avoided since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.5.1
Pseudo-Differential Input
The CS4265 implements a pseudo-differential input stage. The SGND input is intended to be used as a
pseudo-differential reference signal. This feature allows for common mode noise rejection with single-
ended signals. Figure 12 shows a basic diagram outlining the internal implementation of the pseudo-dif-
ferential input stage. The Typical Connection Diagram shows the recommended pseudo-differential input
PGA
MUX
+32 dB
AINA
MICIN1
Channel B
PGA Gain Bits
Out to ADC
Channel A
Out to ADC
Channel B
MUX
+32 dB
AINB
MICIN2
PGA
Analog Input
Selection Bits
Channel A
PGA Gain Bits
Figure 11. Analog Input Architecture
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