參數(shù)資料
型號(hào): CDB4955A
廠商: Cirrus Logic Inc
文件頁數(shù): 30/60頁
文件大?。?/td> 0K
描述: EVALUATION BOARD FOR CS4955A
標(biāo)準(zhǔn)包裝: 1
主要目的: 視頻,視頻處理
嵌入式: 是,其它
已用 IC / 零件: CS4955
主要屬性: NTSC/PAL 數(shù)字視頻編碼器
次要屬性: 圖形用戶界面,RS-232 接口
已供物品:
相關(guān)產(chǎn)品: CS4954-CQZR-ND - IC VID ENCODER NTSC/PAL 48-TQFP
598-1682-ND - IC VIDEO ENCODER NTSC/PAL 48TQFP
CS4954 CS4955
36
DS278F6
8.2
Register Description
A set of internal registers are available for control-
ling the operation of the CS4954/5. The registers
extend from internal address 0×00 through 0×5A.
Table 9 shows a complete list of these registers and
their internal addresses. Note that this table and the
subsequent register description section describe the
full register map for the CS4954 only. A complete
CS4955 register set description is available only to
MacrovisionTM ACP-PPV Licensed Buyers.
8.2.1 Control Registers
PADR
RD
PDAT[7:0]
Trd
Trpw
Trah
Trda
Trdh
Tas
Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle
WR
PADR
PDAT[7:0]
Tas
Twds
Twdh
Twpw
Twr
Twac
Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle
Address
Register Name
Type
Default value
0
×00
control_0
r/w
01h
0
×01
control_1
r/w
02h
0
×02
control_2
r/w
00h
0
×03
control_3
r/w
00h
0
×04
control_4
r/w
3Fh
0
×05
control_5
r/w
00h
0
×06
control_6
r/w
00h
0
×07
RESERVED
0
×08
bkg_color
r/w
03h
Table 9. Control Registers
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