參數(shù)資料
型號(hào)： CDB4364
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 31/50頁(yè)
文件大?。?/td> 0K
描述： EVALUATION BOARD FOR CS4364
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 6
位數(shù)： 24
采樣率（每秒）： 192k
數(shù)據(jù)接口： 串行
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： CS4364
相關(guān)產(chǎn)品： CS4364-CQZR-ND - IC DAC 103DB 24BIT 6CH 48-LQFP
598-1059-ND - IC DAC 103DB 24BIT 6CH 48-LQFP
DS619F1
37
CS4364
6.5
Filter Control (Address 05h)
6.5.1
Interpolation Filter Select (FILT_SEL)
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the Analog characteristics table, and response plots can
be found in Figures 22 to 45.
6.6
Invert Control (Address 06h)
6.6.1
Invert Signal Polarity (INV_xx)
Function:
When set to 1, this bit inverts the signal polarity of channel xx.
When set to 0 (default), this function is disabled.
6.7
Group Control (Address 07h)
6.7.1
Mute Pin Control (MUTEC1, MUTEC0)
Default = 00
00 - Six mute control signals
01, 10 - One mute control signal
11 - Three mute control signals
Function:
Selects how the internal mute control signals are routed to the MUTEC1 through MUTEC6 pins. When
set to ‘00’, there is one mute control signal for each channel: AOUT1A on MUTEC1, AOUT1B on
MUTEC2, etc. When set to ‘01’ or ‘10’, there is a single mute control signal on the MUTEC1 pin. When
set to ‘11’, there are three mute control signals, one for each stereo pair: AOUT1A and AOUT1B on
MUTEC1, AOUT2A and AOUT2B on MUTEC2, and AOUT3A and AOUT3B on MUTEC3.
6.7.2
Channel A Volume = Channel B Volume (Px_A=B)
Default = 0
0 - Disabled
1 - Enabled
7
6
5
432
10
Reserved
FILT_SEL
0
000
00
7
6
5
432
10
Reserved
INV_B3
INV_A3
INV_B2
INV_A2
INV_B1
INV_A1
0
000
00
7
6
5
432
10
MUTEC1
MUTEC0
Reserved
P1_A=B
P2_A=B
P3_A=B
Reserved
SNGLVOL
0
000
00
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