參數(shù)資料
型號(hào)： CDB4364
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 16/50頁(yè)
文件大?。?/td> 0K
描述： EVALUATION BOARD FOR CS4364
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 6
位數(shù)： 24
采樣率（每秒）： 192k
數(shù)據(jù)接口： 串行
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： CS4364
相關(guān)產(chǎn)品： CS4364-CQZR-ND - IC DAC 103DB 24BIT 6CH 48-LQFP
598-1059-ND - IC DAC 103DB 24BIT 6CH 48-LQFP
DS619F1
23
CS4364
4.3.1
OLM #1
OLM #1 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to
SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on SDIN1.
4.3.2
OLM #2
OLM #2 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to
SCLK at 256 Fs. Six channels of MSB first 24-bit PCM data are input on SDIN1.
4.4
Oversampling Modes
The CS4364 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the M4, M3 and M2 pins in Hardware Mode or the FM bits in Software Mode. Single-Speed
Mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode
supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode sup-
ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
The auto speed-mode detect feature allows for the automatic selection of speed mode based off of the in-
coming sample rate. This allows the CS4364 to accept a wide range of sample rates with no external inter-
vention necessary. The auto speed-mode detect feature is available in both Hardware and Software Mode.
LRCK
SCLK
Left Channel
Right Channel
SDINx
654
3
210
987
15 14 13 12 11 10
10
654
3210
98
7
15 14 13 12 11 10
17 16
32 clocks
Figure 13. Format 5 - Right-Justified 18-bit Data
LRCK
SCLK
LSB
MSB
20 clks
64 clks
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
DAC_A1
20 clks
Left Channel
Right Channel
SDIN1
DAC_A2
DAC_A3
DAC_B1
DAC_B2
DAC_B3
Figure 14. Format 8 - One Line Mode 1
LSB
MSB
24 clks
128 clks
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
DAC_A1
24 clks
Left Channel
Right Channel
128 clks
LRCK
SCLK
SDIN1
DAC_A2
DAC_A3
DAC_B1
DAC_B2
DAC_B3
Figure 15. Format 9 - One Line Mode 2
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