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參數(shù)資料
| 型號： | CDB4364 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 19/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD FOR CS4364 |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 6 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | CS4364 |
| 相關(guān)產(chǎn)品： | CS4364-CQZR-ND - IC DAC 103DB 24BIT 6CH 48-LQFP 598-1059-ND - IC DAC 103DB 24BIT 6CH 48-LQFP |
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26
DS619F1
CS4364
Figure 18. DSD Phase Modulation Mode Diagram
4.9
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4364 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the rec-
ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4364 should be connect-
ed to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
4.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same
supply, but a decoupling capacitor should still be placed on each supply pin.
Note:
All decoupling capacitors should be referenced to analog ground.
The CDB4364 evaluation board demonstrates the optimum layout and power supply arrangements.
4.10
Analog Output and Filtering
The CS4364 does not include phase or amplitude compensation for an external filter. Therefore, the DAC
system phase and amplitude response will be dependent on the external analog circuitry.
Figure 19 shows how the full-scale analog output level specification is derived.
Figure 20 shows how the recommended output filtering with location for optional mute circuit.
BCKA
(128Fs)
BCKD
(64Fs)
DSD_SCLK
DSDAx,
DSDBx
D1
D0
D2
D0
DSD_SCLK
DSDAx,
DSDBx
BCKA
(64Fs)
DSD_SCLK
DSD Phase
Modulation Mode
DSD Normal Mode
Not Used
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