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參數(shù)資料
| 型號： | CBTL12131ET |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | DisplayPort multiplexer for bidirectional video in all-in-one computer systems |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-195, SOT543-1, TFBGA-64 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 215K |
| 代理商： | CBTL12131ET |
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CBTL12131
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 25 February 2011
13 of 28
NXP Semiconductors
CBTL12131
DisplayPort multiplexer for bidirectional video
[1]
Steady-state is shown only. A HIGH-to-LOW transition will be filtered (~4 ms delay).
7.5 AUX logic state detection
CBTL12131 includes a helpful function to determine the DC state of the AUX_B_P and
AUX_B_N pins thereby aiding in the detection of devices connected to the external DP
connector. The DC state of these pins is output on pins AUX_B_P_STATE and
AUX_B_N_STATE respectively, after the 1 Mbit/s (typ) Manchester-encoded bitstream is
removed by filtering.
7.6 HPD logic state detection
To further aid in detection of externally connected devices on Port B, the HPD_B_FLT pin
outputs a filtered version of pin HPD_B. The filtering function suppresses the 1 ms (typ)
LOW interrupt pulse from a DisplayPort sink, thereby avoiding a false disconnect
detection. Only a LOW pulse greater than 4 ms will result in a LOW output on
HPD_B_FLT.
7.7 Equalizer
The Equalizer function equalizes the signal on the Main Link channel of Port B and
re-drives them to Port D and ultimately to the internal display panel.
The Equalizer is only active when PATH_SEL is HIGH. When PATH_SEL is LOW, the
equalizer is effectively disabled and presents minimum parasitic load to the Main Link
channels.
The Equalizer has configurable Equalization (EQ) settings for its input (Port B side), which
can be set to one of five options by quinary input pin EQ5. See Table 7 for programming
options.
Table 6.
HPD channel configuration
Inputs
Outputs
Comment
PATH_SEL
HPD_B
HPD_D
HPD_A
HPD_B
HPD_B_FLT[1]
HPD_C
0
high-Z
0
Normal mode; internal display
not (yet) asserting HPD
0
1
0
high-Z
0
1
Normal mode; internal display
asserting HPD
0
1
0
1
high-Z
1
0
Normal mode but unexpected
condition; internal display not
asserting HPD during normal
operation
0
1
high-Z
1
Normal mode; with external sink
asserting HPD
1
n/a
0
External source mode with
internal display not (yet)
asserting HPD
1
n/a
1
0
1
0
External source mode with
internal display asserting HPD
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| CBTL12131ET,518 | 功能描述:編碼器、解碼器、復用器和解復用器 1.1 MUX BI-DRC VIDEO 1 DISPLAYPORT CONN RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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