
CBTL12131
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 25 February 2011
6 of 28
NXP Semiconductors
CBTL12131
DisplayPort multiplexer for bidirectional video
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type
Description
Control inputs
PATH_SEL
E1
3.3 V low-voltage CMOS
single-ended input
Input to set the path configuration of the CBTL12131. When LOW,
Ports A and B are mutually connected, as well as Ports C and D.
When HIGH, Port B is connected to Port D.
DDC_AUX_SEL
D10
3.3 V low-voltage CMOS
single-ended input
Input to select between DDC and AUX terminals for Port A. When
HIGH, the DDC_A_P and DDC_A_N terminals are connected to their
respective AUX_B_P and AUX_B_N terminals on Port B. When
LOW, the AUX_A_P and AUX_A_N terminals are connected to their
respective AUX_B_P and AUX_B_N terminals on Port B.
EQ5
E10
3.3 V low-voltage CMOS
quinary input
Equalizer setting input pin. This pin can be board-strapped to one of
five decode values: short to GND, resistor to GND, open-circuit,
resistor to VDD, short to VDD. See
Table 7 for truth table.
PL5
D9
3.3 V low-voltage CMOS
quinary input
Pre-emphasis level setting input pin. This pin can be board-strapped
to one of five decode values: short to GND, resistor to GND,
open-circuit, resistor to VDD, short to VDD. See
Table 8 for truth
table.
LV5
F9
3.3 V low-voltage CMOS
quinary input
Output differential swing setting input pin. This pin can be
board-strapped to one of five decode values: short to GND, resistor
to GND, open-circuit, resistor to VDD, short to VDD. See
Table 9 for
truth table.
TST_REXT
F1
3.3 V low-voltage CMOS
single-ended input with
current sensing analog
input
Test pin for NXP use, combined with external current sensing
function. Should be tied to ground via an external resistor of value
10 k
Ω± 1 %. This pin must not be left open-circuit to avoid possible
erroneous engagement of test mode in normal operation.
AUX_TERM_SRC G1
3.3 V low-voltage CMOS
single-ended input
Input to enable source-type termination on the Port B AUX pair.
When HIGH, 100 k
Ω termination resistors are applied to the Port B
AUX pair. When LOW, the termination resistors will be disabled
(high-impedance).
AUX_TERM_SNK G2
3.3 V low-voltage CMOS
single-ended input
Input to enable sink-style termination on the Port B AUX pair. When
HIGH, a 500 k
Ω termination resistor to VDD is applied to AUX_B_P.
When LOW, the termination resistor will be disabled
(high-impedance).
Status outputs
HPD_B_FLT
F10
3.3 V low-voltage CMOS
single-ended output
This outputs a filtered version of HPD_B.
AUX_B_P_STATE D1
3.3 V low-voltage CMOS
single-ended output
DC state (HIGH or LOW) of AUX_B_P signal.
AUX_B_N_STATE D2
3.3 V low-voltage CMOS
single-ended output
DC state (HIGH or LOW) of AUX_B_N signal.