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| 型號： | CBTL12131ET |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | DisplayPort multiplexer for bidirectional video in all-in-one computer systems |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-195, SOT543-1, TFBGA-64 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大小： | 215K |
| 代理商： | CBTL12131ET |
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CBTL12131
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 25 February 2011
7 of 28
NXP Semiconductors
CBTL12131
DisplayPort multiplexer for bidirectional video
Port A terminals
ML_A_0P
K7
differential port terminal
Four high-speed differential pairs for DisplayPort Main Link signals,
Port A. Designated as port facing the GPU for external video. Port A
will be exclusively connected to Port B when PATH_SEL = LOW, and
will be high-impedance when PATH_SEL = HIGH.
ML_A_0N
J7
differential port terminal
ML_A_1P
K8
differential port terminal
ML_A_1N
J8
differential port terminal
ML_A_2P
K9
differential port terminal
ML_A_2N
J9
differential port terminal
ML_A_3P
K10
differential port terminal
ML_A_3N
J10
differential port terminal
AUX_A_P
H10
differential port terminal
High-speed differential pair for DisplayPort AUX signals, Port A.
These terminals are active when DDC_AUX_SEL = LOW only;
when DDC_AUX_SEL = HIGH, these are high-impedance.
AUX_A_N
H9
differential port terminal
DDC_A_0
G10
differential port terminal
Port A terminal intended for AUX AC coupling capacitor bypass.
These terminals are active when DDC_AUX_SEL = HIGH only;
when DDC_AUX_SEL = LOW, these are high-impedance.
DDC_A_1
G9
differential port terminal
HPD_A
K6
3.3 V LVTTL
single-ended output
3.3 V LVTTL HPD output for Port A. When PATH_SEL = LOW, this
output follows the state of HPD_B (from external DP or ++DP sink).
When PATH_SEL = HIGH, this output is always LOW.
Port B terminals
ML_B_0P
A7
differential port terminal
Four high-speed differential pairs for DisplayPort Main Link signals,
Port B. Designated as port facing the external DP connector. Port B
will be exclusively connected to Port A when PATH_SEL = LOW and
HPD_B_FLT = HIGH, and will be exclusively connected to Port D
when PATH_SEL = HIGH. When PATH_SEL = HIGH, the signal
ordering and association to Port D ML signals is automatically
corrected by internal routing, to map to the DP connector's inverted
signal ordering for a DP sink-side connector.
ML_B_0N
B7
differential port terminal
ML_B_1P
A8
differential port terminal
ML_B_1N
B8
differential port terminal
ML_B_2P
A9
differential port terminal
ML_B_2N
B9
differential port terminal
ML_B_3P
A10
differential port terminal
ML_B_3N
B10
differential port terminal
AUX_B_P
C10
differential port terminal
High-speed differential pair for DisplayPort AUX signals, Port B.
AUX_B_N
C9
differential port terminal
HPD_B
A6
3.3 V bidirectional
LVTTL I/O with high-Z
state
HPD input with 5 V tolerance or output for Port B, to be connected to
the external DP connector. When PATH_SEL = LOW, HPD_B is
configured as input (from external DP or ++DP sink). When
PATH_SEL = HIGH, HPD_B is configured as output and follows the
state of HPD_D (from internal sink), to be connected via DP
connector to an external DP source.
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CBTL12131ET,518 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 1.1 MUX BI-DRC VIDEO 1 DISPLAYPORT CONN RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CBTL12131ET518 | 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| CBTL1608A1UK,012 | 制造商:NXP Semiconductors 功能描述:PHACBTL1608A1UK,012 IC,HIGH SPEED SWITCH |
| CBTL1608A1UK,019 | 制造商:NXP Semiconductors 功能描述:PHACBTL1608A1UK,019 IC,HIGH SPEED SWITCH |
| CBTL1610A1UKAZ | 制造商:NXP Semiconductors 功能描述:LINEAR IC |
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