參數(shù)資料
型號(hào)： CBTL12131ET
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： DisplayPort multiplexer for bidirectional video in all-in-one computer systems
中文描述： SPECIALTY ANALOG CIRCUIT, PBGA64
封裝： 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-195, SOT543-1, TFBGA-64
文件頁(yè)數(shù)： 28/28頁(yè)
文件大?。?/td> 215K
代理商： CBTL12131ET
CBTL12131
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 25 February 2011
9 of 28
NXP Semiconductors
CBTL12131
DisplayPort multiplexer for bidirectional video
7.
Functional description
7.1 General
The CBTL12131 is a high-bandwidth DisplayPort channel switching device designed for
use in all-in-one computers. It contains high-bandwidth switches arranged between four
Ports (A through D) to allow two different channel topologies, where each channel
comprises a Main Link (ML), AUX and HPD path for comprehensive DisplayPort channel
switching. One can select between two basic configurations: either Ports A and C are
connected to Ports B and D respectively, or Port B is connected to Port D while Ports A
and C are high-impedance. In addition, the CBTL12131 includes circuitry to assist in
detection and configuration of Port B designated as the port facing the external
DisplayPort connector. This section describes these functional blocks in detail.
7.2 Main Link DisplayPort switches/multiplexers
The Main Link path topology provides for four differential pairs in each Port, and an
equalizer for each differential pair in the path from Port B to Port D, as shown in Figure 5.
The Main Link switches are operated by CMOS input PATH_SEL and further qualified by
the state of internally derived signal HPD_B_FLT (see Section 7.6 for details). When
PATH_SEL is LOW, Ports C and D are mutually connected, Ports A and B are mutually
connected only when HPD_B_FLT is HIGH, and the equalizer is turned off (isolating).
When PATH_SEL is HIGH, Ports A and C are disconnected (high-impedance) and Port D
is connected to Port B via the equalizer. The equalizer can by bypassed or configured by
quinary input EQ5 to any of five equalizer settings (including a flat response) depending
on specific application conditions. For details on the Equalizer function, please refer to
Fig 5.
Main Link channel topology
002aae677
PL5
EQ output disabled/no load when PATH_SEL = 0
PATH_SEL = 0: pass
PATH_SEL = 1: off
EQ
ML port A
ML port B
ML port C
ML port D
PATH_SEL = 0 and
HPD_B_FLT = 1: pass
else: off
EQ5
LV5
Table 3.
Main Link channel configuration
Legend: high-Z = isolating, high-impedance; ACT = active, low-impedance.
Inputs
Channels
Comment
PATH_SEL
HPD_B_FLT
Port C - Port D
Port A - Port B
Port B - Port D
0
ACT
high-Z
Normal mode; internal display only
0
1
ACT
high-Z
Normal mode with dual display
1
0
high-Z
ACT
External source mode with internal
display not yet asserting HPD
1
high-Z
ACT
External source mode with internal
display asserting HPD
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