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參數(shù)資料
| 型號(hào)： | CB45000 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS6 STANDARD CELLS |
| 中文描述： | HCMOS6標(biāo)準(zhǔn)單元 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 265K |
| 代理商： | CB45000 |
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CB45000 SERIES
MODULE GENERATORS
A series of module generators using compiled
cell generation techniques, are available to
support a range of megacells. These modules
enable the designer to choose individual
parameters in order to create a compiled cell,
which
meets
the
requirements. These include single port RAM,
dual port RAM and ROM.
specific
application
The compiled cell generators construct custom
cells, which are implemented using a special leaf
cell technique, ensuring predictable layout and
accurate module characteristics. In choosing
megacells the designer can consider the trade-
offs between speed and area to generate a fully
customized cell which meets their specific device
requirements.
MEGACELLS
These megacell generators are complemented
by a group of application specific embedded
megacells. These allow access to technologies
that have been hitherto the domain of standard
products. Examples include mixed mode cells for
graphics, DAC/ADC’s (4-9 bit), PLL applications,
and Digital Signal Processor functions for cellular
comms, fax and high-speed modems, which
initially consist of a Triple 8-bit DAC, Graphics
RAM, Clock Multiplier PLL and Frequency
Synthesis PLL.
100 Mbps serial transputer links coupled with
large and fast memory can be used for pipelining,
Table 5
Module Generator Library
Cell
Description
SPRAM
256K bits max
16K word max 128 bit max
Zero static current, Tristate outputs
DPRAM
256K bits max
16K word max 128 bit max
Zero static current, Tristate outputs
ROM
2M bits max
32K word max 64 bit max
Diffusion programmable, Tristate outputs
caching and synchro circuits in modern RISC
computing architectures. Viterbi and Reed
Solomon cores aim at the HDTV and satellite
transmission markets. To support telecom needs
for CCITT standard applications, ADPCM cells
supporting CT2 protocol have been developed.
DESIGN FOR TESTABILITY
The time and cost for ASIC testing increases
exponentially as the complexity and size of the
ASIC grows. Using a design for testability
methodology allows large, more complex ASICs
to be efficiently and economically tested.
CB45000 supports the JTAG boundary Scan and
both edge and level sensitive scan design
techniques
by
providing
macrocells. Scan testing aids device testability by
permitting access to internal nodes without
requiring a separate external connection for each
node accessed. Testability is assured at device
level with the close coupling of LSSD latch
elements, Automatic Test Pattern Generation
(ATPG)
and
high
architecture. BIST options for memory generators
are also available.
the
necessary
pattern
depth
tester
At system level, SGS-THOMSON fully supports
IEEE 1149.1, and the I/O structure utilized in this
family is completely compatible. Several types of
core scan cells are provided in the CB45000
Series library. Examples include FDxS/FJKxS
cells which are edge sensitive and LSxx cells
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