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參數(shù)資料
| 型號： | CB45000 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS6 STANDARD CELLS |
| 中文描述： | HCMOS6標準單元 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 265K |
| 代理商： | CB45000 |
CB45000 SERIES
HCMOS6 STANDARD CELLS
March 1998
1/16
FEATURES
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0.35 micron 5 layer metal HCMOS6 process,
retrograde well technology, low resistance
salicided active areas and polysilicide gates.
3.3 V optimized transistor with 5 V I/O inter-
face capability
2 - input NAND delay of 160 ps (typ) with
fanout = 2.
Broad I/O functionality including Low Voltage
CMOS, Low Voltage TTL and LVDS. Driving
capability to ISA, EISA, PCI, MCA, and SCSI
interface levels
High drive I/O; capability of sinking up to 24
mA with slew rate control, current spike sup-
pression and impedance matching.
Generators to support Single Port RAM,
Dual Port RAM, and ROM with BIST options.
DRAM integration in ASIC methodology
Extensive embedded function library includ-
ing ST DSP and micro cores, third party
micros and Synopsys synthetic libraries.
Fully independent power and ground config-
urations for inputs, core and outputs.
I/O ring capability up to 1000 pads.
Latchup trigger current > +/- 500 mA.
ESD protection > +/- 4000 volts typical value
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Oscillators for wide frequency spectrum.
Broad range of 500+ SSI cells
Design For Test features including IEEE
1149.1 JTAG Boundary Scan architecture.
Cadence, Mentor and Synopsys based
design systems with interfaces from multiple
workstations.
Broad ceramic and plastic package range.
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CB45000 Super-Integration
Cost Effective Product
Architecture Partitioning
Trouble free integration
Application Specific
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Your Product is Unique
User specified cell integration
Design Confidentiality
IP fully re-usable
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DSP
ST20
DPRAM
ROM
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