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參數(shù)資料
| 型號： | CB45000 |
| 廠商： | 意法半導體 |
| 英文描述： | HCMOS6 STANDARD CELLS |
| 中文描述： | HCMOS6標準單元 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 265K |
| 代理商： | CB45000 |
CB45000 SERIES
4/16
LIBRARY
The CB45000 Series library is organized into four
categories:
SSI cell library
IO Cell library
Macrofunctions
Module generators
I
I
I
I
SSI CELL LIBRARY OVERVIEW
The design of the CB45000 family has been
optimized to allow extremely high density, high
speed and low power designs. For these reasons
a wide range of cells with different ranges of
driving capability are available in the library.
The library cells have been optimized in term of
functional and electrical parameters in order to
have:
Good balancing
Maximum speed
Optimum Threshold voltage
10 êm
I
I
I
I
Symmetric Vdd/Vss Noise margin
Minimum Power-Speed figure
The geometrical aspect of the cells was
configured to allow extremely dense design, fully
exploiting the features of the Place and Route
tool in terms of horizontal and vertical routing
grids. For Place and Route, up to five levels of
metal are utilized. Intracell wiring is limited as far
as possible to first metal, with second, third and
fourth metal levels dedicated to interconnect
wiring and power distribution. The fifth metal is
used for power and clock bussing.
I
CORE LOGIC
The propagation delays shown in the CB45000
data book are given for nominal processing, 3.3V
operation, and 25 C temperature conditions.
However there are additional factors that affect
the delay characteristics of the macrocells. These
include loading due to fanout and interconnect
routing, voltage supply, junction temperature of
the device, processing tolerance and input signal
transition time.
Prior to physical layout, the design system can
estimate the delays associated with any critical
path. The impact of the placement and routing
can be accurately RC back annotated from the
layout for final simulations of critical timing. The
effects of junction temperature, (K
T
) and voltage
supply (K
V
) on the delay numbers are
summarized in Table 2 and Table 2. A third factor,
is associated with process variation. This
multiplier has a minimum of 0.8 and a maximum
of 1.2.
Figure 2. ND2 Core Cell
Table 1 Junction Temperature Multipliers
Temperature
o
C
K
T
-55
0.77
-40
0.83
25
1.00
70
1.13
85
1.17
125
1.27
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