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參數(shù)資料
| 型號(hào)： | CB45000 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS6 STANDARD CELLS |
| 中文描述： | HCMOS6標(biāo)準(zhǔn)單元 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 265K |
| 代理商： | CB45000 |
CB45000 SERIES
6/16
important as the packaging options become ever
broader.
The pad size and pitch are not determined until
the customers choice of packaging, signal
interface standards and I/O count is considered.
Wire bond pad spacings down to 65
μ
and 50
μ
centres will released in the near future to support
large signal counts without die area loss.
All pads except the sixteen corner pads can be
configured as power or I/O pads. The configured
power pads are known as placeable pads and
have an associated current handling capability.
Their placement is dependent on the types of
output buffers used in the design. For rules
governing the placement of pads, please contact
your local SGS-THOMSON design centre.
I/O TEST INTERFACE
The IO cells have a dedicated test interface to
facilitate parametric and Iddq testing of devices.
This test interface connects standard core signals
or dedicated test signals to the IO cells allowing
all Output Buffers to be driven high, low or put
into tristate regardless of the state of the internal
logic.
This greatly simplifies parametric testing of the
part and also assisting customers who wish to
use this feature during board testing. Note that all
output buffers can be tristated by this function
including buffers that normally do not tristate.
This test function also turns off all pull up or down
devices and shuts down all differential receivers
and converts them into standard CMOS
receivers. This allows Iddq test methodologies to
be employed in a very efficient way, avoiding
unneeded circuit overhead.
Inside the IO cell is a section of specialized
transistors used to create the receiver functions.
A full set of standard receivers with pull up and
pull down devices is present in the library. The
technologies supported match the output buffer
capabilities and include, LVCMOS, LVTTL, GTL,
CTL, Differential, etc. and a five volt interface
capability.
MACROCELLS AND MACROFUNCTIONS
The CB45000 series has internal macrocells that
are robust in variety and performance. The cell
selection has been driven by the need of
Synthesis and HDL based design techniques.
This offering is rich in buffers, complex
combinatorial cells and multi power drive cells,
which allow the Synthesis tool to create a netlist
compatible with the requirements of Place and
Route tools.
Macrofunctions are a series of soft-macros
facilitating quick capture of large functional blocks
and are available for such functions as counters,
shift register and adders. Macrofunctions are
implemented at layout by utilizing macrocells and
interconnecting to create the logic function.
Table 3
I/O Drive Capacity for LVCMOS and
LVTTL Slew Rate Buffers
Current Drive
(mA)
Maximum
Capacitance (pF)
2.0
50
4.0
100
8.0
200
12.0
300
16.0
400
Table 4
I/O Drive Capacity for LVCMOS and
LVTTL Non Slew Rate Buffers
Current Drive
(mA)
Maximum
Capacitance (pF)
2.0
50
4.0
100
8.0
200
12.0
300
16.0
400
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