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參數(shù)資料
| 型號： | BXM80526B600128 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 600 MHz, MICROPROCESSOR, PBGA495 |
| 封裝： | BGA2-495 |
| 文件頁數(shù)： | 61/74頁 |
| 文件大?。?/td> | 870K |
| 代理商： | BXM80526B600128 |
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Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
57
PICCLK (I - 2.5V Tolerant)
The PICCLK (APIC Clock) signal is an input clock to the processor and system logic or I/O APIC
that is required for operation of the processor, system logic, and I/O APIC components on the
APIC bus.
PICD[1:0] (I/O - 1.5V Tolerant Open-drain)
The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC
bus. They must be connected to the appropriate pins/balls of all APIC bus agents, including the
processor and the system logic or I/O APIC components. If the PICD0 signal is sampled low on
the active-to-inactive transition of the RESET# signal, then the APIC is hardware disabled.
PLL1, PLL2 (Analog)
The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL.
See Section 3.2.2 for a description of the analog decoupling circuit.
PRDY# (O - GTL+)
The PRDY# (Probe Ready) signal is a processor output used by debug tools to determine
processor debug readiness.
PREQ# (I - 1.5V Tolerant)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the
processor.
PWRGOOD (I - 2.5V Tolerant)
PWRGOOD (Power Good) is a 2.5-V tolerant input. The processor requires this signal to be a
clean indication that clocks and the power supplies (VCC, VCCT, etc.) are stable and within their
specifications. Clean implies that the signal will remain low, (capable of sinking leakage current)
and without glitches, from the time that the power supplies are turned on, until they come within
specification. The signal will then transition monotonically to a high (2.5V) state. Figure 24
illustrates the relationship of PWRGOOD to other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before the rising edge of
be followed by a 1 ms RESET# pulse.
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