參數(shù)資料
型號： BXM80526B600128
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 600 MHz, MICROPROCESSOR, PBGA495
封裝： BGA2-495
文件頁數(shù)： 54/74頁
文件大?。?/td> 870K
代理商： BXM80526B600128
Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
51
8.0
Processor Interface
8.1
Alphabetical Signal Reference
A[35:3]# (I/O - GTL+)
The A[35:3]# (Address) signals define a 2
36-byte physical memory address space. When ADS# is
active, these signals transmit the address of a transaction; when ADS# is inactive, these signals
transmit transaction information. These signals must be connected to the appropriate pins/balls of
both agents on the system bus. The A[35:24]# signals are protected with the AP1# parity signal,
and the A[23:3]# signals are protected with the AP0# parity signal.
On the active-to-inactive transition of RESET#, each processor bus agent samples A[35:3]#
signals to determine its power-on configuration. See Section 7.0 of this document and the
Pentium
II Processor Developer’s Manual for details.
A20M# (I - 1.5V Tolerant)
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal cache and before driving a read/write
transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at
the 1-Mbyte boundary. Assertion of A20M# is only supported in Real mode.
ADS# (I/O - GTL+)
The ADS# (Address Strobe) signal is asserted to indicate the validity of a transaction address on
the A[35:3]# signals. Both bus agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop or deferred reply ID match operations
associated with the new transaction. This signal must be connected to the appropriate pins/balls on
both agents on the system bus.
AERR# (I/O - GTL+)
The AERR# (Address Parity Error) signal is observed and driven by both system bus agents, and
if used, must be connected to the appropriate pins/balls of both agents on the system bus. AERR#
observation is optionally enabled during power-on configuration; if enabled, a valid assertion of
AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent may handle an
assertion of AERR# as appropriate to the error handling architecture of the system.
AP[1:0]# (I/O - GTL+)
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#,
A[35:3]#, REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. A correct parity
signal is high if an even number of covered signals are low and low if an odd number of covered
相關(guān)PDF資料
PDF描述
BXM80526B700128 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495
BXM80526B700 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495
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