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| 型號(hào)： | BX80562X3230SLACS |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 266 MHz, MICROPROCESSOR, PBGA775 |
| 封裝： | LGA-775 |
| 文件頁數(shù)： | 82/96頁 |
| 文件大?。?/td> | 1398K |
| 代理商： | BX80562X3230SLACS |
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Quad-Core Intel Xeon Processor 3200 Series Datasheet
83
Features
6
Features
6.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 6-1.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a "power-on" reset.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 6-1 for a visual representation of the processor low
power states.
Table 6-1.
Power-On Configuration Option Signals
Configuration Option
Signal1,2,3
Notes:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address signals not identified in this table as configuration options should not
be asserted during RESET#.
3. Disabling of any of the cores within the processor must be handled by
configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow
for the disabling of a single core per die within the package.
Output tristate
SMI#
Execute BIST
A3#
Disable dynamic bus parking
A25#
Symmetric agent arbitration ID
BR0#
RESERVED
A[8:5]#, A[24:4]#, A[35:26]#
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