
Quad-Core Intel Xeon Processor 3200 Series Datasheet
27
Electrical Specifications
Note:
1.
VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
3.
The input buffers use a Schmitt-triggered input design for improved noise immunity.
Table 2-11. CMOS Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
VIL
Input Low Voltage
-0.10
VTT * 0.30
V
2, 3
2.
VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3.
The VTT referred to in these specifications refers to instantaneous VTT.
VIH
Input High Voltage
VTT * 0.70
VTT + 0.10
V
4.
VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5.
VIH and VOH may experience excursions above VTT.
VOL
Output Low Voltage
-0.10
VTT * 0.10
V
VOH
Output High Voltage
0.90 * VTT
VTT + 0.10
V
6.
All outputs are open drain.
IOL
Output Low Current
1.70
4.70
mA
7.
IOL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT.
IOH
Output High Current
1.70
4.70
mA
ILI
Input Leakage Current
N/A
± 100
A
8
8.
Leakage to VSS with land held at VTT.
ILO
Output Leakage Current
N/A
± 100
A
9
9.
Leakage to VTT with land held at 300 mV
Table 2-12. PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes
Vin
Input Voltage Range
-0.30
VTT
V
Vhysteresi
s
Hysteresis
0.1 * VTT
—V
3
Vn
Negative-edge threshold voltage
0.275 * VTT
0.500 * VTT
V
Vp
Positive-edge threshold voltage
0.550 * VTT
0.725 * VTT
V
Isource
High level output source
(VOH = 0.75 * VTT)
-6.0
N/A
mA
Isink
Low level output sink
(VOL = 0.25 * VTT)
0.5
1.0
mA
Ileak+
High impedance state leakage to VTT
N/A
50
A
2
Ileak-
High impedance leakage to GND
N/A
10
A
2
Cbus
Bus capacitance
—10
pF
Vnoise
Signal noise immunity above 300 MHz
0.1 * VTT
—Vp-p