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參數(shù)資料
| 型號： | BX80538T1400 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1830 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | MICRO, FCPGA-478 |
| 文件頁數(shù)： | 3/91頁 |
| 文件大?。?/td> | 2017K |
| 代理商： | BX80538T1400 |
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Datasheet
11
Low Power Features
2
Low Power Features
2.1
Clock Control and Low Power States
The Intel Core Duo processor and Intel Core Solo processor support low power states
both at the individual core level and the package level for optimal power management.
A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low
power states. Refer to Figure 2 for a visual representation of the core low power states
for the Intel Core Duo processor and Intel Core Solo processor. When both cores
coincide in a common core low power state, the central power management logic
ensures the Intel Core Duo processor enters the respective package low power state by
initiating a P_LVLx (P_LVL2, P_LVL3, and P_LVL4) I/O read to the Mobile Intel 945
Express Chipset family. Package low power states include Normal, Stop Grant, Stop
Grant Snoop, Sleep, Deep Sleep, and Deeper Sleep. Refer Figure 1 for a visual
representation of the package low-power states for the Intel Core Duo processor and
Intel Core Solo processor and to Table 1 for a mapping of core low power states to
package low power states.
The processor implements two software interfaces for requesting low power states:
MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK
register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are
converted to equivalent MWAIT C-state requests inside the processor and do not
directly result in I/O reads on the processor FSB. The monitor address does not need to
be setup before using the P_LVLx I/O read interface. The sub-state hints used for each
P_LVLx read can be configured in a software programmable MSR.
When software running on a core requests the C4 state, that core enters the core C4
state, which is identical to the core C3 state. When both cores have requested C4 then
the Intel Core Duo processor will enter the Deeper Sleep state.
If a core encounters a chipset break event while STPCLK# is asserted, then it asserts
the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to
system logic that individual cores should return to the C0 state and the Intel Core Duo
processor should return to the Normal state. Same mechanism is also applicable for the
Intel Core Solo processor.
NOTE:
1.
AutoHALT or MWAIT/C1.
Table 1.
Coordination of Core-Level Low Power States at the Package Level
Resolved
Package State
Single
Core
Dual Core: Core1 State
C0
C11
C2
C3
C4
Core0
/
Functi
onal
Co
re
S
tate
C0
Normal
C1
Normal
C2
Stop Grant
Normal
Stop Grant
C3
Deep Sleep
Normal
Stop Grant
Deep Sleep
C4
Deeper Sleep
Normal
Stop Grant
Deep Sleep
Deeper Sleep /
Intel
Enhanced
Deeper Sleep
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