參數(shù)資料
型號(hào)： BX80532RC2400B
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 2400 MHz, MICROPROCESSOR
文件頁(yè)數(shù)： 75/99頁(yè)
文件大小： 4142K
代理商： BX80532RC2400B
Datasheet
77
Pin Listing and Signal Definitions
PROCHOT#
Input/
Output
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain
active until the system deasserts PROCHOT#. See Section 7.3 for more details.
NOTE:
The PROCHOT# signal is input/output only on CPUID 0xF27 and
beyond; otherwise, it is an output signal.
PWRGOOD
Input
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. ‘Clean’ implies that the signal will remain low (capable
of sinking leakage current), without anomalies, from the time that the power
supplies are turned on until they come within specification. The signal must then
transition monotonically to a high state. Figure 14 illustrates the relationship of
PWRGOOD to the RESET# signal. PWRGOOD can be driven inactive at any
time, but clocks and power must again be stable before a subsequent rising edge
of PWRGOOD. It must also meet the minimum pulse width specification in
Table 19, and be followed by a 1 to 10 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins of all
processor system bus agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are source
synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for details on
parity checking of these signals.
RESET#
Input
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least one millisecond after VCC
and BCLK have reached their proper specifications. On observing active
RESET#, all system bus agents will deassert their outputs within two clocks.
RESET# must not be kept asserted for more than 10 ms while PWRGOOD is
asserted.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in the Section 7.1.
NOTE:
This signal does not have on-die termination and must be terminated on
the system board.
RS[2:0]#
Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RSP#
Input
RSP# (Response Parity) is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection. It must connect to the
appropriate pins of all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low, and
low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is
also high, since this indicates it is not being driven by any agent guaranteeing
correct parity.
SKTOCC#
Output
SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System
board designers may use this pin to determine if the processor is present.
Table 36. Signal Description (Sheet 6 of 8)
Name
Type
Description
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