參數(shù)資料
型號(hào)： BX80532RC2400B
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 2400 MHz, MICROPROCESSOR
文件頁(yè)數(shù)： 22/99頁(yè)
文件大小： 4142K
代理商： BX80532RC2400B
Datasheet
29
Electrical Specifications
2.13
System Bus AC Specifications
The processor system bus timings specified in this section are defined at the processor silicon.
See Chapter 5.0 for the Celeron processor on 0.13 micron process pin signal definitions.
Table 16 through Table 21 list the AC specifications associated with the processor system bus. All
AGTL+ timings are referenced to GTLREF for both ‘0’ and ‘1’ logic levels unless otherwise
specified.
AGTL+ layout guidelines are available in the appropriate Platform Design Guide (see Table 1).
Care should be taken to read all notes associated with a particular timing parameter.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2).
3. For the clock jitter specification, refer to the CK408 Clock Design Guidelines.
4. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
5. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
4. Valid delay timings for these signals are specified into the test circuit described in Figure 6 and with GTLREF
at 2/3 VCC ± 2%.
5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate
of 0.4 V/ns to 4.0 V/ns.
6. RESET# can be asserted asynchronously, but must be deasserted synchronously.
7. This should be measured after VCC and BCLK[1:0] become stable
8. Maximum specification applies only while PWRGOOD is asserted.
.
Table 16. System Bus Differential Clock Specifications
T# Parameter
Min
Nom
Max
Unit
Figure
Notes1
System Bus Frequency
100
MHz
T1: BCLK[1:0] Period
10.0
10.2
ns
2
T2: BCLK[1:0] Period Stability
200
ps
3, 4
T3: BCLK[1:0] High Time
3.94
5
6.12
ns
T4: BCLK[1:0] Low Time
3.94
5
6.12
ns
T5: BCLK[1:0] Rise Time
175
700
ps
5
T6: BCLK[1:0] Fall Time
175
700
ps
5
Table 17. System Bus Common Clock AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes1,2,3
T10: Common Clock Output Valid Delay
0.12
1.27
ns
4
T11: Common Clock Input Setup Time
0.65
ns
5
T12: Common Clock Input Hold Time
0.40
ns
5
T13: RESET# Pulse Width
1
10
ms
6, 7, 8
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