參數(shù)資料
型號(hào)： BX80532RC2400B
廠(chǎng)商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 2400 MHz, MICROPROCESSOR
文件頁(yè)數(shù)： 36/99頁(yè)
文件大?。?/td> 4142K
代理商： BX80532RC2400B
Datasheet
41
System Bus Signal Quality Specifications
3.0
System Bus Signal Quality Specifications
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI)
effects. For these reasons, it is important that the designer work to achieve a solution that provides
acceptable signal quality across all systematic variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation and for interpreting results for signal quality measurements of actual designs.
3.1
System Bus Clock (BCLK) Signal Quality Specifications
Table 23 describes the signal quality specifications at the processor core silicon for the processor
system bus clock (BCLK) signals. Figure 21 describes the signal quality waveform for the system
bus clock at the processor core silicon.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor on 0.13 micron process
frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Table 23. BCLK Signal Quality Specifications
Parameter
Min
Max
Unit
Figure
Notes1
BCLK[1:0] Overshoot
N/A
0.30
V
BCLK[1:0] Undershoot
N/A
0.30
V
BCLK[1:0] Ringback Margin
0.20
N/A
V
2
BCLK[1:0] Threshold Region
N/A
0.10
V
Figure 21. BCLK Signal Integrity Waveform
Crossing
Voltage
Threshold
Region
VH
VL
Overshoot
Undershoot
Ringback
Margin
Rising Edge
Ringback
Falling Edge
Ringback,
BCLK0
BCLK1
Crossing
Voltage
相關(guān)PDF資料
PDF描述
BU-61559D1-230W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-61559D1-230 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-61559D1-260Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-61559D1-340Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-61559D1-660Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BX80532RC2500B 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.5GHZ 478-PIN FCPGA2 - Boxed Product (Development Kits)
BX80532RC2600B 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.6GHZ - Boxed Product (Development Kits)
BX80532RC2800B 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.8GHZ - Boxed Product (Development Kits)
BX80536NC1700EJ 制造商:Intel 功能描述:MPU CELERON PROCESSOR 390 RISC 64-BIT 90NM 1.7GHZ 1.05V - Boxed Product (Development Kits)
BX80537T5500 S L9SH 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5500 64-Bit 65nm 1.66GHz 1.05V 478-Pin FCPGA6
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