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參數(shù)資料
| 型號(hào)： | BX80532KC1900E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1900 MHz, MICROPROCESSOR |
| 文件頁數(shù)： | 62/132頁 |
| 文件大小： | 2316K |
| 代理商： | BX80532KC1900E |
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Intel Xeon Processor MP with up to 2MB L3 Cache
2-21
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5 * Vcc at the processor pins. All TAP
signal timings (TMS, TDI, etc) are referenced at the 0.5 * Vcc processor pins.
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
5. Referenced to the rising edge of TCK.
6. Referenced to the falling edge of TCK.
7. Specification for a minimum swing defined between TAP 20% to 80%. This assumes a minimum edge rate of
0.5 V/ns
8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
9. It is recommended that TMS be asserted while TRST# is being deasserted.
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All AC timings for the SMBus signals are referenced at VIL_MAX or VIH_MIN and measured at the processor
pins. Refer to Figure 16.
4. Minimum time allowed between request cycles.
5. Rise time is measured from (VIL_MAX - 0.15 V) to (VIH_MIN + 0.15 V). Fall time is measured from (0.9 *
Table 20. TAP Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,3,9
T55: TCK Period
60.0
ns
T56: TCK Rise Time
9.5
ns
4
T57: TCK Fall Time
9.5
ns
4
T58: TMS, TDI Rise Time
8.5
ns
4
T59: TMS, TDI Fall Time
8.5
ns
4
T61: TDI, TMS Setup Time
0
ns
5, 7
T62: TDI, TMS Hold Time
3.0
ns
5,7
T63: TDO Clock to Output Delay
0.5
3.5
ns
6
T64: TRST# Assert Time
2.0
TTCK
8
Table 21. SMBus Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes1,2,3
T70: SM_CLK Frequency
10
100
KHz
T71: SM_CLK Period
10
100
s
T72: SM_CLK High Time
4.0
N/A
s
T73: SM_CLK Low Time
4.7
N/A
s
T74: SMBus Rise Time
0.02
1.0
s
5
T75: SMBus Fall Time
0.02
0.3
s
5
T76: SMBus Output Valid Delay
0.1
4.5
s
T77: SMBus Input Setup Time
250
N/A
ns
T78: SMBus Input Hold Time
300
N/A
ns
T79: Bus Free Time
4.7
N/A
s
4, 6
T80: Hold Time after Repeated Start Condition
4.0
N/A
s
T81: Repeated Start Condition Setup Time
4.7
N/A
s
T82: Stop Condition Setup Time
4.0
N/A
s
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