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參數(shù)資料
| 型號： | BX80532KC1900E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1900 MHz, MICROPROCESSOR |
| 文件頁數(shù)： | 28/132頁 |
| 文件大?。?/td> | 2316K |
| 代理商： | BX80532KC1900E |
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Intel Xeon Processor MP with up to 2MB L3 Cache
9-25
REQ[4:0]#
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor
system bus agents. They are asserted by the current bus owner to define the
currently active transaction type. These signals are source synchronous to
ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking
of these signals.
RESET#
I
Asserting the RESET# signal resets all processors to known states and invalidates
their internal caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCC and BCLK
have reached their proper specifications. On observing active RESET#, all system
bus agents will deassert their outputs within two clocks. RESET# must not be kept
asserted for more than 10ms.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
RS[2:0]#
I
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RSP#
I
RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect to the appropriate pins of all
processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
SKTOCC#
O
SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate
that the processor is present.
SLP#
I
SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the
Sleep state. During Sleep state, the processor stops providing internal clock signals
to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in
this state will not recognize snoops or interrupts. The processor will recognize only
assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK
input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop-Grant state, restarting its internal clock signals to the bus and
processor core units.
SMB_PRT
O
SMB_PRT (SMBus Present) pin is grounded on processor packages (FC-mPGA2)
that do not contain SMBus components (PIROM, Scratch EEPROM, and thermal
sensor). It is floating on processor packages (INT-mPGA) that do contain the
SMBus components.
SM_ALERT#
O
SM_ALERT# (SMBus Alert) is an asynchronous interrupt line associated with the
SMBus Thermal Sensor device. It is an open-drain output and the processor
includes a 10k
pull-up resistor to SM_V
CC for this signal. It is only available on the
Intel Xeon processor in INT-mPGA package. For more information on the usage of
the SM_ALERT# pin, see Section 6.4.5.
SM_CLK
I/O
The SM_CLK (SMBus Clock) signal is an input clock to the system management
logic which is required for operation of the system management features of the Intel
Xeon processor MP on the 0.13 micron process processor. This clock is driven by
the SMBus controller and is asynchronous to other clocks in the processor.The
processor includes a 10 k
pull-up resistor to SM_V
CC for this signal. It is only
available on the Intel Xeon processor in INT-mPGA package.
SM_DAT
I/O
The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal
provides the single-bit mechanism for
transferring data
between
SMBus
devices.The processor includes a 10 k
pull-up resistor to SM_V
CC for this signal.
It is only available on the Intel Xeon processor in INT-mPGA package.
Table 52. Signal Definitions (Sheet 7 of 9)
Name
Type
Description
相關PDF資料 |
PDF描述 |
|---|---|
| BU-61582D0-290S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D0-300K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-391Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-410S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-431 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80532KC2000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
| BX80532KC2000E | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
| BX80532KC2200DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.2GHZ 603-PIN IN - Boxed Product (Development Kits) |
| BX80532KC2400D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
| BX80532KC2400DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
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