參數(shù)資料
型號： BX80532KC1900E
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 1900 MHz, MICROPROCESSOR
文件頁數(shù)： 39/132頁
文件大?。?/td> 2316K
代理商： BX80532KC1900E
Introduction
1-4
Intel Xeon Processor MP with up to 2MB L3 Cache
Retention mechanism - The support components that are mounted through the baseboard to
the chassis to provide mechanical retention for the processor and heatsink assembly.
Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory) - A
memory device located on the Intel Xeon processor MP with up to 2-MB L3 cache processor
and the Intel Xeon processor in INT-mPGA package, addressable via the SMBus which can be
used by the OEM to store information (e.g., information for system management, etc). See
Section 6.4 for details on the Scratch EEPROM.
SMBus - System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the system. It is based on
the principals of the operation of the I2C two-wire serial bus from Philips Semiconductor.
1.2
References
Material and concepts available in the following documents may be beneficial when reading this
document.
NOTES:.
1. Available electronically on the Intel Developer public website http://developer.intel.com
2. Available electronically on the www.sbs-forum.org/smbus.
§
Document
Number/Location
AP-485, Intel Processor Identification and the CPUID Instruction
241618
IA-32 Intel Architecture Software Developer's Manual
1. Volume I: Basic Architecture
2. Volume II: Instruction Set Reference
3. Volume III: System Programming Guide
245470
245471
245472
CK00 Clock Synthesizer/Driver Design Guidelines
249206
VRM 9.1 DC-DC Converter Design Guidelines
298646
Intel Xeon Processor Multiprocessor Platform Design Guide
250397
Intel Xeon Processor (MP) Thermal Design Guidelines
298650
603 -Pin Socket Design Guidelines
249672
Intel Xeon Processor MP Family Enabled Components ProE* Files
http://developer.intel.com
Intel Xeon Processor MP Family Enabled Components IGES Files
http://developer.intel.com
Intel Xeon Processor MP with 512-KB L2 Cache Core Boundary Scan
Descriptor Language (BSDL) Model (V1.1) and Cell Descriptor File (V1.0)
http://developer.intel.com
ITP 700 Debug Port Design Guide
249679
System Management Bus Specification, rev 1.1
www.sbs-forum.org/smbus
Wired for Management 2.0 Design Guide
http://developer.intel.com
相關PDF資料
PDF描述
BU-61582D0-290S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-61582D0-300K 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-61582D1-391Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-61582D1-410S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-61582D1-431 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
相關代理商/技術參數(shù)
參數(shù)描述
BX80532KC2000D 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits)
BX80532KC2000E 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits)
BX80532KC2200DU 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.2GHZ 603-PIN IN - Boxed Product (Development Kits)
BX80532KC2400D 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits)
BX80532KC2400DU 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits)
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