參數(shù)資料
型號: BUS-65164-130K
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70
封裝: 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70
文件頁數(shù): 7/40頁
文件大?。?/td> 349K
代理商: BUS-65164-130K
15
Notes:
1)IF ADDR_ENA IS LOGIC “1”, CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED
(DT_ACK = LOGIC “0”).
2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t13 ARE DEFINED AS THE FALLING EDGE OF
DT_REQ.
3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t12 ARE DEFINED AS THE RISING EDGE OF DT_REQ.
4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES.
MID-PARITY
STATUS
MID-SYNC
DATA
MID-PARITY
t14
MID-PARITY
PRESENT COMMAND
t11
t16
t9
CWC=2
t12
t13
CWC=1
t12
t13
t9
CWC=0
t15
t17
t18
FIGURE 5. BC TO RT (RECEIVE) TIMING
150
100
190
140
3.29
3.17
3.37
3.23
3.46
3.26
3.57
3.36
100
6.76
6.0
1.94
6.96
ns
GBR PULSE WIDTH
t18(@16MHz
GBR PULSE WIDTH
t18(@12MHz)
s
MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLING
t17(@16MHz)
s
MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLING
t16(@12MHz)
s
MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISING
t16(@16MHz)
s
MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISING
t16(@12MHz
s
MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISING
t15
s
RT RESPONSE TIME
t14(@16MHz)
ms
s
MID-PARITY CROSSING OF RECEIVED DATA WORD TO START OF DATA TRANSFER CYCLE (Note 2)
RT RESPONSE TIME
t13(@12MHz)
t14(@12MHz)
ns
t12
UNITS
TYP
DESCRIPTION
SYMBOL
1.52
6.18
60
MAX
MIN
END OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3)
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