- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄210357 > BUS-65164-130K (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 PDF資料下載
參數(shù)資料
| 型號(hào)： | BUS-65164-130K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70 |
| 文件頁(yè)數(shù)： | 17/40頁(yè) |
| 文件大?。?/td> | 349K |
| 代理商： | BUS-65164-130K |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)
24
,
,
t1
t12
t2
t4
t6
t8
t5
t7
t10
t9
valid
t3
DT_REQ
DT_GRT
DT_ACK
WR
(SEE NOTE 1)
CS
(SEE NOTE 1)
A05-A01
DB15-DB00
(OUTPUT)
ADDR. WINDOW
(SEE NOTE 1)
t11
,
MAX
3.0
SYMBOL
t12
TYP
t1(@12MHz)
DT_ACK HIGH DELAY TO ADDRESS, WRT, CS TRI-STATE (Note 1)
DMA REQUEST TO DMA GRANT (COMMAND WORD)
s
t1(@16MHz)
DMA REQUEST TO DMA GRANT (COMMAND WORD)
s
t1(@12MHz)
ns
DMA REQUEST TO DMA GRANT (DATA WORD)
s
t1(@16MHz)
DMA REQUEST TO DMA GRANT (DATA WORD)
s
t2
DMA GRANT PULSE WIDTH
ns
t3
DMA GRANT DELAY TO DMA ACKNOWLEDGE
ns
t4
DT_ACK PULSE WIDTH
ns
t5
DT_ACK LOW DELAY TO ADDRESS ENABLED (Note 1)
ns
t6(@12MHz)
DT_ACK LOW DELAY TO RISING EDGE OF CS
ns
t6(@16MHz)
DT_ACK LOW DELAY TO RISING EDGE OF CS
ns
t7(@12MHz)
DATA VALID SETUP TIME TO RISING EDGE OF CS
ns
t7(@16MHz)
DATA VALID SETUP TIME TO RISING EDGE OF CS
ns
t8(@12MHz)
45
CS LOW PULSE WIDTH
ns
t8(@16MHz)
CS LOW PULSE WIDTH
ns
t9(@12MHz)
DATA HOLD TIME FOLLOWING RISING EDGE OF CS
ns
t9(@16MHz)
DATA HOLD TIME FOLLOWING RISING EDGE OF CS
ns
t10
DATA TRI-STATE SETUP TIME PRIOR TO RISING EDGE OF DT_REQ, DT_ACK
ns
t11
DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1)
ns
3.3
3.5
3.7
130
485
515
35
315
365
360
410
195
255
150
185
170
205
70
50
10
60
FIGURE 10. DMA WRITE 16-BIT
Note:
1)Diagram assumes ADDR_ENA is set to logic “0”. If is was set to logic “1”, then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as
shown by “ADDR. WINDOW” timing.
DESCRIPTION
MIN
UNITS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BUS-65164-180K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61743F3-100W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61743F3-202L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61743F3-202W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61743F3-280L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-S802 | 制造商:Fuji Electric 功能描述: |
| BU-S803 | 制造商:Fuji Electric 功能描述: |
| BUS98 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SITCHMODE Series NPN Silicon Power Transistors |
| BUS98/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SWITCHMODE? Series NPN Silicon Power Transistors |
| BUS98A | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SITCHMODE Series NPN Silicon Power Transistors |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。