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參數(shù)資料
| 型號： | BUS-65164-130K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70 |
| 文件頁數(shù)： | 37/40頁 |
| 文件大?。?/td> | 349K |
| 代理商： | BUS-65164-130K |
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6
D00
D01
WC 0
WC 1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
4Kx1
PROM
SA 2
WC 2
WC 3
SA 3
SA 4
T/R
WC 4
SA 0
SA 1
A07
A10
A11
A08
A09
A12
D02
D03
D04
BUS-65153
"STIC"
A13
ILLEGAL
_______
BRO
A11
OE
__
D0
CS
__
Q
D
Q
state mode, based on broadcast, T/R bit, subaddress, and word
count requires an external latch to store the value of the word
count field. The word count must be latched after the address
lines A5...A1 are updated for the present command and before
these address lines are cleared to 00000 for the command word
transfer.
The word count address lines (A5...A1) are multiplexed internal-
ly between the latched word count field of the command word,
and the current word counter. While the signal INCMD is high
(logic 1) these address lines reflect the word count field of the
present command. While INCMD is low (logic 0) these signals
represent the value of the current word counter, which is cleared
to zero at the start of a message, and is incremented after each
data word transfer.
The output of the illegalization PROM may be latched using a
flip-flop and an AND gate (see FIGURE 2). The output signal
INCMD from the STIC is used as the clock enable input to the
flip-flop. The flip-flop is updated on every rising clock edge while
INCMD is high, and is not updated while INCMD is low. This
allows the output of the PROM to be updated on the last clock
edge before INCMD is asserted low. Once INCMD is asserted,
the clock enable input to the flip-flop is removed, thus preserving
the value of the latched illegal bit.
Illegalizing commands in the three-state mode of operation also
requires the use of a latch. The latch must be updated during a
word transfer since the address lines are normally in a high
impedance state. FIGURE 3 illustrates a method of latching the
output from the PROM using a flip-flop and the signal CS.
The signal CS is driven low during every word transfer. The only
word transfer that takes place before the illegal command input
(ILLCMD) input is sampled is the command word transfer. The
word count field of the command word may be obtained directly
from the lower 5 bits of the data bus. The subaddress, T/R, and
broadcast signals are available on address lines A07-A13. Note
that the signal CS will be asserted twice during a transfer in the
8-bit mode of operation. The word count field is located in the
lower byte, which is presented during the second byte transfer.
The second CS will, therefore, latch the appropriate value for
ILLEGAL.
FIGURE 3. BUS-65153 THREE-STATE ILLEGALIZATION
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