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參數(shù)資料
| 型號： | BUS-65164-110S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70 |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 349K |
| 代理商： | BUS-65164-110S |
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shared RAM for each broadcast / T-R bit / subaddress / mode
code.
If a more elaborate shared RAM interface is needed, the BUS-
65153 may be interfaced to a BUS-66315 memory management
unit. If a BUS-66315 is used, the address bus of the BUS-65153
is not used for accessing the system RAM (although the address
outputs may still be used for command illegalizing).
The BUS-66315 provides an RT Lookup Table, allowing the
mapping of the various T-R/subaddresses to user programmable
areas in the BUS-66315's 64K x 16 shared RAM address space.
The BUS-66315 also provides a stack area of RAM. The stack
provides a chronology of all messages processed, storing a
Block Status Word (message channel, completion, and validity
information), an optional Time Tag Word and the received
Command Word for each message processed. The BUS-66315
also provides maskable interrupts to the host processor for end-
of-message and/or message error conditions.
ADDRESS MAPPING
The memory allocation scheme for the BUS-65153 14-bit
address bus is defined as follows:
A13:
BROADCAST/OWNADDRESS
A12:
TRANSMIT/RECEIVE
A11-A7: SUBADDRESS 4-0
A6:
DATA/COMMAND
A5-A1:
WORD COUNT/CURRENT WORD COUNT
A0:
UPPER/LOWER BYTE (8-bit mode only)
The method of address mapping implemented by the BUS-
65153 provides for a “mailbox” allocation scheme for the storage
of Command and Data Words. The address outputs A13 through
A1 map directly into 8K words (16K bytes) of processor address
space. A0 is used for upper/lower byte selection in the 8-bit DMA
mode. The same address map is applicable for both the DMA
and shared RAM (without the BUS-66315) interface configura-
tions. The BUS-65153's addressing scheme maps messages in
terms of broadcast/own address, transmit/receive, subaddress,
and mode code. A 64-word message block is allocated for each
T/R-subaddress.
The received Command Word for all nonmode code messages
is stored at relative word location zero (0) within the respective
message block. For mode code messages, the address for the
received Command Word is offset from location zero (0) within
the message block for subaddress 0 or 31. The value of the
address offset is equal to the mode code field of the respective
Command Word (0 to 31).
For nonmode code messages, the Data Words to be transmitted
or received are accessed from (to) relative locations 32 through
63 within the message block. For mode code messages with a
single Data Word that is not read from internal register, the
address for the Data Word is offest from location 32 within the
64-word message block for subaddresses 0 and 31. The value
of the address offset is equal to the mode code field of the
received Command Word.
The Data Words transmitted in response to Transmit Last
Command or Transmit BIT Word mode commands are accessed
from a pair of internal registers.
DMA INTERFACE
An 8/16-bit data bus, a 14-bit address bus, and six control sig-
nals are provided to facilitate communication with the parallel
subsystem. The control signals include the standard DMA hand-
shake signals DT_REQ, DT_GRT, DT_ACK as well as the trans-
fer control outputs CS and WRT. HS_FAIL provides an indication
to the subsystem of a handshake failure condition.
Data is transferred between the subsystem and the BUS-65153
via a DMA handshake, initiated by the BUS-65153. A READ
operation is defined to be the transfer of data from the subsys-
tem to the BUS-65153. Conversely, a WRITE operation transfers
data from the BUS-65153 to the subsystem.
If the BUS-65153 is in 16-bit mode, data is transferred as a sin-
gle 16-bit word. In 8-bit mode, data is transferred in a pair of byte
transfers within the same DMA handshake cycle. The upper byte
is transferred first with A0=1, followed by the lower byte with
A0=0.
HANDSHAKE FAIL
If the BUS-65153 (STIC) asserts DT_REQ and the subsystem
does not respond with DT_GRT in time for the BUS-65153 to
complete the word transfer, the HS_FAIL output will be asserted
low to inform the subsystem of the handshake failure and bit D12
in the internal Built-In-Test (BIT) word is set to logic 1." If the
handshake failure occurs on a data word read transfer (transmit
command) the STIC will abort the current message processing
and NOT transmit erroneous data back to the bus controller. In
the case of a handshake failure on a write transfer (receive com-
mand word transfer, transmit command transfer, or a receive
data word transfer) the STIC will set the handshake failure out-
put and BIT word bit, and continue processing the current mes-
sage.
DMA READ OPERATION
Whenever the BUS-65153 needs to read a word from the sub-
system, it asserts the signal DT_REQ low. If the subsystem
asserts DT_GRT in time, the BUS-65153 will then assert A13
through A1 (and A0 for the 8-bit mode), WRT high, along with
DT_ACK and CS low to enable data from the subsystem.
After the transfer of each Data Word has been completed,
address bus outputs A5 through A1 are incremented. This pro-
vides the option of connecting the BUS-65153 address lines
directly to the host processor's address bus to access the sub-
system RAM, if desired.
DMA WRITE OPERATION
Whenever the BUS-65153 needs to transfer data to the subsys-
tem, it initiates a DMA WRITE cycle. The BUS-65153 asserts
DT_REQ. The subsystem must respond with DT_GRT.
If DT_GRT was received in time, the BUS-65153 will then assert
DT_ACK. The BUS-65153 will then assert A13 through A1 (and
4
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