參數(shù)資料
型號(hào): BUS-65164-110S
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70
封裝: 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70
文件頁(yè)數(shù): 12/40頁(yè)
文件大?。?/td> 349K
代理商: BUS-65164-110S
2
TABLE 1. BUS-65153 SPECIFICATIONS
PARAMETER
MIN
MAX
- 0.3
- 0.5
+ 0.3
- 0.5
11
0.500
k
pF
VP-P
VPEAK
6
20
18
-250
100
22
21
150
9
27
10
250
300
0.8
20
0.4
0.5
3.4
4.5
-15.75
4.5
-12.6
5
65
20
55
90
160
5.5
-14.25
5.5
-11.4
115
50
112
175
300
V
mA
ABSOLUTE MAXIMUN RATINGS
Supply Voltage
n Logic + 5V
Transceiver + 5 V
n - 15 V
n - 12 V
Logic
n Voltage Input Range
V
TYP
UNITS
LOGIC
VIH
VIL
IIH (VIN=VCC)
IIL (VIN=GND)
VOH (IOH = 0)
VOH (IOH = max)
VOL (IOL = 0)
VOL (IOL = min)
IOL
IOH
RECEIVER
Differential Input Resistance
n (Bus-65153, Bus-65163,
BUS- 65154, Bus-65164)
(Notes 1 - 6)
Differential Input Capacitance
n (Bus-65153, Bus-65163,
BUS-65154, Bus-65164)
(Notes 1 - 6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
VP-P
mV
P
-P,diff
mV
nsec
TABLE 1. BUS-65153 SPECIFICATIONS
PARAMETER
MIN
TYP
POWER SUPPLY REQUIREMENTS
(CONTINUED)
Current Drain
(BUS-65154, BUS-65164, Note 9)
n + 5 V Logic (CH A, CH B)
n - 12 V (CH A, CH B)
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
65
30
87
135
230
115
60
120
185
305
mA
POWER DISSIPATION
BUS-65153, BUS-65163
n Total Hybrid
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
n Hottest Die
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
BUS-65154, BUS-65164
n Total Hybrid
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
n Hottest Die
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
0.625
0.850
1.075
1.525
0.335
0.600
0.860
1.385
0.685
0.985
1.285
1.885
0.290
0.590
0.890
1.490
1.325
1.963
2.600
3.875
0.68
1.06
1.45
2.23
1.295
1.727
2.160
3.035
0.59
0.92
1.36
2.16
W
16.0
12.0
33
40
0.01
0.1
0.001
0.01
67
60
MHz
%
THERMAL
Thermal Resistance, Junction-to-
Case, Hottest Die (
θJC)
n BUS-65153, BUS-65163
n BUS-65154, BUS-65164
Operating Junction Temperature
Storage Temperature
Lead Temperature
(Soldering for 10 seconds)
1553 MESSAGE TIMING
RT Response Time
16 MHz
12 MHz
RT-to-RT No Response Timeout
(Note 8)
Transmitter Watchdog Timeout
-55
-65
6.00
6.18
18.25
6.5
18.9
668
160
150
+300
6.96
6.76
19.5
°C/W
°C
S
CLOCK INPUT
Frequency
n Nominal Value (Selectavle)
CLOCKSEL Input = Logic ‘0’
CLOCKSEL Input = Logic ‘1’
n Long Term Tolerance
1553A Compliance
1553B Compliance
n Short Term Tolerance, 1 Second
1553A Compliance
1553B Compliance
Duty Cycle
16 MHz
12 MHz
5.54
UNITS
MAX
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
(BUS-65153, BUS-65163)
n + 5 V (Logic)
n + 5 V (CH A, CH B)
n - 15 V (CH A, CH B)
Voltages/Tolerances
(BUS-65154, BUS-65164)
n + 5 V (Logic)
n + 5 V (CH A, CH B)
n - 12 V (CH A, CH B)
Current Drain
(BUS-65153, BUS-65163, Note 9)
n + 5 V Logic (CH A, CH B)
n - 15 V (CH A, CH B)
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
TRANSMITTER
Differential Output Voltage
n Direct Coupled Accross 35 ohms,
Measured on Bus
n Direct Coupled Accross 70 ohms
Measured on Stub
BUS-65153, BUS-65163 (Note 10)
BUS-65154, BUS-65164
Output Noise, Differential
(Direct Coupled)
Output Offset Voltage, Transformer
Coupled Accross 70 Ohms
Rise/Fall Time
2.0
-20
Vcc+0.4
3.7
-3.4
10
0.860
10
7.0
- 18.0
Vcc+0.5
V
Α
V
mA
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