參數(shù)資料
型號(hào): BUS-65164-110S
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70
封裝: 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70
文件頁(yè)數(shù): 20/40頁(yè)
文件大?。?/td> 349K
代理商: BUS-65164-110S
27
,
,
t1
t2
t4
t5
t7
valid
t3
DT_REQ
DT_GRT
DT_ACK
WR
(SEE NOTE 1)
CS
(SEE NOTE 1)
A05-A01
DB15-DB00
(OUTPUT)
ADDR. WINDOW
(SEE NOTE 1)
t11
t8
A00
UPPER BYTE
(15..8)
LOWER BYTE
(7..0)
valid
,
,
,
,
,
t6
t9
t10
t3
t6
t9
t10
MIN
MAX
15.1
SYMBOL
112
DESCRIPTION
TYP
UNITS
t1(@12MHz)
DT_ACK HIGH DELAY TO ADDRESS, WRT, CS TRI-STATE (Note 1)
DMA REQUEST TO DMA GRANT
s
t1(@16MHz)
DMA REQUEST TO DMA GRAN)
s
t6(@16MHz)
ns
START OF BYTE TRANSFER CYCLE TO FALLING EDGE OF CS
ns
50
t5
95
t2
DT_ACK DELAY TO A0 LOW (UPPER BYTE TRANSFER CYCLE TIME)
DMA GRANT PULSE WIDTH
ns
t3
DMA GRANT DELAY TO DMA ACKNOWLEDGE
ns
t4
ns
485
515
t6(@12MHz)
START OF BYTE TRANSFER CYCLE TO FALLING EDGE OF CS
ns
t7
DT_ACK LOW DELAY TO ADDRESS, WRT, CS ENABLED (Note 1)
ns
t8(@12MHz)
45
CS PULSE WIDTH
ns
t8(@16MHz)
CS PULSE WIDTH
ns
t10
DATA HOLD TIME FOLLOWING CS HIGH
ns
t11
DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1)
ns
15.3
130
985
1015
70
115
35
315
345
360
390
0
60
Note:
1)Diagram assumes ADDR_ENA is set to logic “0”. If is was set to logic “1”, then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as
shown by “ADDR. WINDOW” timing
FIGURE 13. DMA READ 8-BIT
DT_ACK PULSE WIDTHACK PULSE WIDTH
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