參數(shù)資料
型號(hào)： BT457KPJ80
英文描述： Video DAC with Color Palette (RAMDAC)
中文描述： 視頻DAC的調(diào)色板（的RAMDAC）
文件頁(yè)數(shù)： 41/60頁(yè)
文件大?。?/td> 647K
代理商： BT457KPJ80
Bt457/Bt458
4.0 Application Information
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
4.6 Initializing the Bt457 (Color) 24-bit MPU
L45801 Rev. N
Conexant
4-9
4.6 Initializing the Bt457 (Color) 24-bit MPU
Data Bus
In this example, three Bt457s are used in parallel to generate true color. A 24-bit
MPU data bus is available to access all three Bt457s in parallel.
The operation and initialization are the same as the monochrome application
of the Bt457.
4.7 Initializing the Bt457 (Color) 8-bit MPU Data
Bus
In this example, three Bt457s are used in parallel to generate true color. An 8-bit
MPU data bus is available to access the Bt457s.
While accessing the command, read mask, blink mask, and control/test and
address registers, each Bt457 must be accessed individually. While accessing the
color palette RAM or overlay registers, all three Bt457s are accessed
simultaneously.
Following a power-on sequence, the Bt457s must be initialized. If the
clock/LD* sequence is controlled to reset the pipeline delay of the Bt457s to a
fixed pipeline delay of eight clock cycles, this initialization sequence must be
performed after the reset sequence. The command register must also be
reinitialized when the multiplex selection changes (e.g., from 4:1 to 5:1 input
multiplexing).
This sequence configures the Bt457s as follows:
4:1 Multiplexed Operation
No Overlays
No Blinking
Each Bt457 initialized as a red, green, or blue device
Control Register Initialization
Red Bt457
Write $04 to address register
Write $FF to read mask register
Write $05 to address register
Write $00 to blink mask register
Write $06 to address register
Write $40 to command register
Write $07 to address register
Write $00 to test register
C1,C0
00
10
00
10
00
10
00
10
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