參數(shù)資料
型號(hào): BT457KPJ80
英文描述: Video DAC with Color Palette (RAMDAC)
中文描述: 視頻DAC的調(diào)色板(的RAMDAC)
文件頁(yè)數(shù): 22/60頁(yè)
文件大小: 647K
代理商: BT457KPJ80
2.0 Registers
Bt457/Bt458
2.4 Bt458 Test Register
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
2-4
Conexant
L45801 Rev. N
inputs are contained in the upper four bits, and the lower four bits contain the red,
green, blue, and low or high nibble enable information previously written. Either
the CLOCK must be slowed down to the MPU cycle time, or the same pixel and
overlay data must be presented to the device during the entire MPU read cycle.
For example, to read the upper four bits of red color information being
presented to the D/A converters, the MPU writes to the test register, setting only
the red enable bit. The MPU then reads the test register, keeping the pixel data
stable, which results in D[7:4] containing R[7:4] color bits and D[3:0] containing
red, green, blue, and low or high nibble enable information, as illustrated below:
D[7]
D[6]
D[5]
D[4]
R7
R6
R5
R4
D[3]
D[2]
D[1]
D[0]
0
0
0
1
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