參數(shù)資料
型號： BT457KPJ80
英文描述： Video DAC with Color Palette (RAMDAC)
中文描述： 視頻DAC的調(diào)色板（的RAMDAC）
文件頁數(shù)： 15/60頁
文件大?。?/td> 647K
代理商： BT457KPJ80
Bt457/Bt458
1.0 Circuit Description
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
1.3 MPU Interface
L45801 Rev. N
Conexant
1-7
When accessing the color palette RAM, the address register resets to $00 after
a blue read or write cycle to location $FF. When accessing the overlay registers,
the address register increments to $04 following a blue read or write cycle to
overlay register three. To keep track of the red, green, and blue read/write cycles,
the address register has two additional bits that count modulo three. They are reset
to 0 when the MPU reads or writes to the address register. The MPU does not
have access to these bits. The other 8 bits of the address register (ADDR[7:0]) are
accessible to the MPU.
Bt457 Reading/Writing
Color Data
(Normal Mode)
To write color data, the MPU loads the address register with the address of the
color palette RAM location or overlay register to be modified. The MPU
performs a color write cycle, using C0 and C1 to select either the color palette
RAM or the overlay registers. The address register then increments to the next
location, which the MPU can modify by writing another color.
Reading color data is similar to writing it, except the MPU executes read
cycles.
This mode is useful if a 24-bit data bus is available, because 24 bits of color
information (8 bits each of red, green, and blue) can be read or written to three
Bt457s in a single MPU cycle. In this application, the CE* inputs of all three
Bt457s are connected together. If only an 8-bit data bus is available, the CE*
inputs must be individually selected during the appropriate color write cycle (red
CE* during red write cycle, blue CE* during blue write cycle, and green CE*
during green write cycle).
When accessing the color palette RAM, the address register resets to $00 after
a read or write cycle to location $FF. When accessing the overlay registers, the
address register increments to $04 following a read or write cycle to overlay
register three.
Bt457 Reading/Writing
Color Data (RGB Mode)
To write color data, the MPU loads the address register with the address of the
color palette RAM location or overlay register to be modified. The MPU
performs three successive write cycles (8 bits each of red, green, and blue), using
C0 and C1 to select either the color palette RAM or the overlay registers. After
the blue write cycle, the address register then increments to the next location,
which the MPU can modify by writing another sequence of red, green, and blue
data. Reading color data is similar to writing it, except the MPU executes read
cycles.
This mode is useful if only an 8-bit data bus is available. Each Bt457 is
programmed to be a red, green, or blue RAMDAC and responds only to the
assigned color read or write cycle. In this application, the Bt457s share a common
8-bit data bus. The CE* inputs of all three Bt457s must be asserted
simultaneously only during color read/write cycles and address register write
cycles.
When accessing the color palette RAM, the address register resets to $00 after
a blue read or write cycle to location $FF. When accessing the overlay registers,
the address register increments to $04 following a blue read or write cycle to
overlay register three. To keep track of the red, green, and blue read/write cycles,
the address register has two additional bits that count modulo three. They are reset
to 0 when the MPU reads or writes to the address register. The MPU does not
have access to these bits. The other 8 bits of the address register (ADDR[7:0]) are
accessible to the MPU.
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