參數(shù)資料
型號(hào)： BT457KPJ80
英文描述： Video DAC with Color Palette (RAMDAC)
中文描述： 視頻DAC的調(diào)色板（的RAMDAC）
文件頁(yè)數(shù)： 36/60頁(yè)
文件大?。?/td> 647K
代理商： BT457KPJ80
4.0 Application Information
Bt457/Bt458
4.1 Clock Interfacing
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
4-4
Conexant
L45801 Rev. N
Subpixel synchronization is supported by the PLL output. Essentially, PLL
provides a signal to indicate the amount of analog output delay of the Bt457
relative to CLOCK. The Bt439 compares the phase of the PLL signals generated
by up to four Bt457s, and adjusts the phase of each of the CLOCK and CLOCK*
signals to the Bt457s to minimize the PLL phase difference. There should be
minimal layout skew in the CLOCK and PLL trace paths to ensure proper clock
alignment.
If subpixel synchronization of multiple Bt457s is not necessary, the Bt438
Clock Generator Chip can be used rather than the Bt439. In this instance, the
CLOCK, CLOCK*, and LD* inputs of up to four Bt457s are connected together
and driven by a single Bt438 (daisy chain with single balanced termination for
<100 MHz or through a 10H116 buffer for >100 MHz). The VREF inputs of the
Bt457s must still have a 0.1 μF bypass capacitor to VAA. The PLL outputs would
not be used and should be connected to GND (either directly or through a resistor
up to 150
).
Figure 4-3. Generating the Bt457 Clock Signals (Color Application)
7
+5V
14
MONITOR
PRODUCTS
970E
220
330
+5V
+5V
+5V
2.2K
430
2N3904
TO
Bt439
70
FROM
Bt457
220
150
PLL0
CLOCK 0
CLOCK 0*
PLL1
CLOCK1
CLOCK1*
PLL2
CLOCK 2
CLOCK2*
LD
VREF
Bt439
Bt457
#1
Bt457
#2
Bt457
#3
PLL
CLOCK
CLOCK*
PLL
CLOCK
CLOCK*
PLL
CLOCK
CLOCK*
LD*
VREF
LD*
VREF
Q1
R1
R2
R1
R1
R1
R1
R1
R2
R2
R2
Q1
Q1
Q1
R1
VAA
VAA
VAA
457-8_009
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