參數(shù)資料
型號: BQ2060SS
英文描述: Silicon Bridge Rectifiers
中文描述: 集成電路表面貼裝,棉絮電荷監(jiān)視器
文件頁數(shù): 38/46頁
文件大小: 364K
代理商: BQ2060SS
CPE
The CPE bit enables/disables PEC transmissions to the
Smart Battery Charger for master mode alarm mes-
sages.
0
NoPEC byte on alarm warning to charge
1
PEC byte on alarm warning to charger
LED
The LED bit configures the bq2060 for 4 or 5 LED
indication
0
Selects the 5 LED indication mode
1
Selects the 4 LED indication mode
SC
The SC bit enables learning cycle optimization for a
Smart Charger or independent charge
0
Learning cycleoptimized forindependent charger
1
Learning cycleoptimized forSmart Charger
SM
The SM bit enables/disables master mode broadcasts by
the bq2060
0
Broadcasts to host and charger enabled
1
Broadcasts to host and charger disabled
If the SB bit is set, modifications to bits in
BatteryMode() will not re-enable broadcasts.
Measurement Calibration
ADC
To describe how the bq2060 calculates reported battery
and individual cell voltages, the following abbreviations
and designations are used:
VCELL
1–4
= voltages at the input pins of the
bq2060
VCELL1–4=reported cellvoltages
Vnl–4 = voltages at the different series nodes in the
battery
Voltage() =reported battery voltage
V
sr
=voltage across the sense resistor
The reported voltages measurements, Voltage() and
VCELL1–4, may be calibrated by adjusting five 8- or
16-bit registers in EEPROM:
ADC Offset
in EE0x62,
ADC Voltage Gain
in EE 0x66–0x67,
Cell 2 Calibration
Factor
in EE 0x63,
Cell 3Calibration Factor
in EE 0x64,
and
Cell4CalibrationFactorin
EE 0x65.
The bq2060 first computes the node voltages Vnl, Vn2,
Vn3, and Vn4. The node voltages are inputs to the volt-
age dividers to the VCELL
1
through VCELL
4
input pins
of the bq2060. The bq2060 computes node voltages to
calculate the five reported voltages by the bq2060: Volt-
age(),VCELL1,VCELL2,VCELL3,and VCELL4.
An
ADC Voltage Gain
factor of 20,000 is the nominal
value when using the recommended cell-voltage division
ratios of 16:1 on the VCELL
4
and VCELL
3
inputs and
8:1 on the VCELL
2
and VCELL
1
inputs. The bq2060
subtracts the voltage across the sense resistor from the
measurements so that the reported voltages reflect the
cell-stack voltages only.
The bq2060 compute the node voltages as
(27)
Vn
VCELL
1
1
32768
1250
ADC Offset
ADC Voltage Gain
65536
(28)
Vn2
VCELL
2
32768
1250
ADC Voltage Gain
ADC Offset
Cell
(
CalibrationFactor
8
65536
2
)
(29)
Vn3
VCELL
3
32768
1250
ADC Voltage Gain
ADC Offset
Cell
(
CalibrationFactor
8
2
65536
)
3
(30)
Vn4
VCELL
4
32768
1250
ADC Voltage Gain
ADC Offset
Cell
(
CalibrationFactor
8
2
65536
)
4
Note:
With LCC1-LCC0 = 00,
Cell 4 Calibration
Factor
=0.
ADC Offset
adjusts the ADC offset for voltage and cur-
rent measurements.
ADC Offset is
a signed 8-bit value
that cancels offset present in the circuit with no poten-
tial or current flow.
ADC Offset is
typically set between
-10and 10.
38
bq2060
Preliminary
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