
ASIX ELECTRONICS CORPORATION
2
CONFIDENTIAL
AX88872P Swipeater Controller PRELIMINARY
CONTENTS
1.0 AX88872 OVERVIEW....................................................................................................................................... 4
1.1 G
ENERAL
D
ESCRIPTION
...................................................................................................................................... 4
1.2 AX88872 B
LOCK
D
IAGRAM
:.............................................................................................................................. 5
1.3 P
IN
C
ONNECTION
D
IAGRAM
............................................................................................................................... 6
2.0 PIN DESCRIPTION........................................................................................................................................... 7
2.1 RMII
INTERFACE FOR REPEATER PORTS
............................................................................................................... 7
2.1.1 Repeater Port 0.......................................................................................................................................... 7
2.1.2 Repeater Port 1.......................................................................................................................................... 7
2.1.3 Repeater Port 2.......................................................................................................................................... 8
2.1.4 Repeater Port 3.......................................................................................................................................... 8
2.1.5 Repeater Port 4.......................................................................................................................................... 8
2.1.6 Repeater Port 5.......................................................................................................................................... 8
2.1.7 Repeater Port 6.......................................................................................................................................... 9
2.1.8 Repeater Port 7.......................................................................................................................................... 9
2.2 MII/RMII
INTERFACE FOR SWITCH PORTS
........................................................................................................... 9
2.2.1 Switch Port 0.............................................................................................................................................. 9
2.2.2 Switch Port 1............................................................................................................................................ 10
2.3 E
XPANSION
B
US
I
NTERFACE FOR
100 M
BPS
....................................................................................................... 11
2.4 E
XPANSION
B
US
I
NTERFACE FOR
10 M
BPS
......................................................................................................... 11
2.5 LED D
ISPLAY
.................................................................................................................................................. 12
2.6 B
UFFER MEMORY PINS GROUP
........................................................................................................................... 13
2.7
M
ISCELLANEOUS
.............................................................................................................................................. 14
2.8 P
OWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE
................................................................ 15
3.0 FUNCTIONAL DESCRIPTION...................................................................................................................... 18
3.1 R
EPEATER
S
TATE
M
ACHINE
.............................................................................................................................. 18
3.2 RXE /TXE C
ONTROL
...................................................................................................................................... 18
3.3 J
ABBER
S
TATE
M
ACHINE
.................................................................................................................................. 18
3.4 P
ARTITION
S
TATE
M
ACHINE
............................................................................................................................. 18
3.5 O
PERATION OF THE
B
UILT
-I
N
S
WITCH
............................................................................................................... 19
3.5.1 Packet Filtering and Forwarding Process ................................................................................................ 19
3.5.2 MAC Address Learning and Aging Process.............................................................................................. 19
3.5.3 Flow Control Process............................................................................................................................... 19
3.6 LED D
ISPLAY
I
NTERFACE
................................................................................................................................ 20
4.0 INTERNAL REGISTERS................................................................................................................................ 22
5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 23
5.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
........................................................................................................................ 23
5.2 G
ENERAL
O
PERATION
C
ONDITIONS
................................................................................................................... 23
5.3 DC C
HARACTERISTICS
..................................................................................................................................... 23
5.4 AC
SPECIFICATIONS
......................................................................................................................................... 24
5.4.1 LCLK....................................................................................................................................................... 24
5.4.2 Reset Timing............................................................................................................................................ 24
5.4.3 RMII Interface Timing TX & RX............................................................................................................... 25
5.4.4 MII Interface Timing TX & RX................................................................................................................. 26
5.4.5 SRAM read cycle...................................................................................................................................... 27
5.4.6 SRAM write cycle..................................................................................................................................... 28
5.4.7 LED DISPLAY ......................................................................................................................................... 29
5.4.8 LED Display after Reset........................................................................................................................... 29