參數(shù)資料
型號(hào)： AX88872P
廠商： ASIX Electronics Corporation
英文描述： 10/100BASE Dual Speed “Swipeater” Controller
中文描述： 一個(gè)10/100Base雙速“Swipeater”控制器
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 399K
代理商： AX88872P
ASIX ELECTRONICS CORPORATION
14
CONFIDENTIAL
AX88872P Swipeater Controller PRELIMINARY
2.7 Miscellaneous
Signal Name
LCLK
/RST
Type Pin No.
I
I
Description
70
59
Local Clock :
50-66Mhz. Used for system operation synchronous.
Reset :
Active Low
The chip is reset when this signal is asserted Low
Reference clock :
The input is a continuous clock at 50Mhz for timing
reference with RMII interface.
Repeater Identification Number Daisy-Chain In :
When MODE=
”
1
”
,
This pin is a daisy chain serial input for Repeater ID. The State machines
always monitors the input if a correct data (RID) present at the pin, the
(RID+1) will be written to RID register and override the power on setup RID
for the chip.
Repeater Identification Number Daisy-Chain Out :
When MODE=
”
1
”
,
This pin is periodically shift out the RID of itself to the next chained chip to
inform that this ID has already been occupied. The RID is shift out
periodically every about 200us.
Station Management Data In/Out :
For setup PHY auto-negotiation
registers. A burst write commands are issue to setup PHY register after reset.
The PHY address 4h, 5h, 6h, 7h, 8h, 9h,Ah and Bh will be written as register
4h to value 00A1h ( Advertise register set to 10/100 half-duplex mode)and
register 0h to value 1000h(Enable auto-negotiation). See also Appendix for
more information.
Station Management Data Clock Out :
For MDIO reference clock.
Test Pin :
Active LOW
The pin is just for test mode setting purpose only. Must be pull high when
normal operation.
NC :
Keep no connection
POWER :
+3.3V +/-5%
REF_CLK
I
68
DAISY_IN
I/PU
73
DAISY_OUT
O/ML
74
MDIO
I/O
57
MDC
/TEST
O
56
58
I/PU
NC
VDD
O
I
157
25, 48
69, 92
122, 144
107, 120
8, 35
67, 71
83, 101
112,115
127, 139
149, 174
185, 208
VSS
I
POWER:
0V
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