參數(shù)資料
型號(hào)： AX88872P
廠商： ASIX Electronics Corporation
英文描述： 10/100BASE Dual Speed “Swipeater” Controller
中文描述： 一個(gè)10/100Base雙速“Swipeater”控制器
文件頁(yè)數(shù)： 11/36頁(yè)
文件大?。?/td> 399K
代理商： AX88872P
ASIX ELECTRONICS CORPORATION
11
CONFIDENTIAL
AX88872P Swipeater Controller PRELIMINARY
2.3 Expansion Bus Interface for 100 Mbps
Signal Name
Type Pin No.
HIRD[3:0]
I/O/Z
/PU
154, 153
Description
156, 155
INTER REPEATER DATA :
Nibble data input/output. Transfer data from
the “active” AX88872/3 to all other “inactive” AX88872/3 chips. The bus-
master of the IRD bus is determined by IR_ACT bus arbitration.
INTER REPEATER DATA VALID :
This signal reflects the RX_DV
status of the active port. Used to frame good packets.
INTER REPEATER CLOCK VALID :
All inter repeater signals are
synchronized to the rising edge of this clock.
INTER REPEATER DATA IN/OUT DIRECTION :
This pin indicates the direction of IRD data .
“High” = HIRD[3:0], /HIRD_V , HIRD_CK are Output.
“Low” = HIRD[3:0], /HIRD_V , HIRD_CK are Input.
LOCAL REPEATER ACTIVITY IN/OUT :
the function is the same as
/HIR_ACTO[3:0] but for local repeater activity only.
INTER REPEATER ACTIVITY IN:
These pins perform the same
function as /HIR_ACTO[3:0] when they serve as input function. Then the
/HIR_ACTO[3:0] insert external buffers the input function must be replaced
with /HIR_ACTI [3:0].
INTER REPEATER ACTIVITY IN/OUT:
The local repeater activity
appearance, the signal of the related RID (Repeater ID) will be asserted and
as an output pin. All other pins serve as input pins but except the collision
conditions. When collision occurs , the signal of related (RID-1) pins will
also serve as outputs and will active during local collision period. The
exception case is when RID = 0, then (RID-1) is replaced with (RID+1).
/HIRD_V
I/O/Z
/PU
I/O/Z
/PU
O
152
HIRD_CK
151
HIRD_ODIR
150
/LHIR_ACT[2:0]
I/O/OC 128, 126
125
/HIR_ACTI[3:0]
I/PU
132, 131
130, 129
/HIR_ACTO[3:0]
I/O/OC 148, 147
146, 145
2.4 Expansion Bus Interface for 10 Mbps
Signal Name
Type Pin No.
TIRD[3:0]
I/O/Z
/PU
103, 102
Description
106, 105
INTER REPEATER DATA :
Nibble data input/output. Transfer data from
the “active” AX88872/3 to all other “inactive” AX88872/3 chips. The bus-
master of the IRD bus is determined by IR_ACT bus arbitration.
INTER REPEATER DATA VALID :
This signal reflects the RX_DV
status of the active port. Used to frame good packets.
INTER REPEATER CLOCK VALID :
All inter repeater signals are
synchronized to the rising edge of this clock.
INTER REPEATER DATA IN/OUT DIRECTION :
This pin indicates the direction of data for external transceiver.
“High” = TIRD[3:0], /TIRD_V , TIRD_CK are Output.
“Low” = TIRD[3:0], /TIRD_V , TIRD_CK are Input.
LOCAL REPEATER ACTIVITY IN/OUT :
the function is the same as
/TIR_ACTO[3:0] but for local repeater activity only.
INTER REPEATER ACTIVITY IN:
These pins perform the same
function as /HIR_ACTO[3:0] when they serve as input function. Then the
/HIR_ACTO[3:0] insert external buffers the input function must be replaced
with /HIR_ACTI [3:0].
INTER REPEATER ACTIVITY IN/OUT:
The local repeater activity
appearance, the signal of the related RID (Repeater ID) will be asserted and
as an output pin. All other pins serve as input pins but except the collision
conditions. When collision occurs , the signal of related (RID-1) pins will
also serve as outputs and will active during local collision period. The
exception case is when RID = 0, then (RID-1) is replaced with (RID+1).
/TIRD_V
I/O/Z
/PU
I/O/Z
/PU
O
100
TIRD_CK
99
TIRD_ODIR
95
/LTIR_ACT[2:0]
I/O/OC 109, 108
107
/TIR_ACTI[3:0]
I/PU
119, 118
117, 116
/TIR_ACTO[3:0]
I/O/OC 124, 123
121,120
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