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參數(shù)資料
| 型號： | AX88872P |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | 10/100BASE Dual Speed “Swipeater” Controller |
| 中文描述： | 一個10/100Base雙速“Swipeater”控制器 |
| 文件頁數(shù)： | 19/36頁 |
| 文件大?。?/td> | 399K |
| 代理商： | AX88872P |
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ASIX ELECTRONICS CORPORATION
19
CONFIDENTIAL
AX88872P Swipeater Controller PRELIMINARY
collision, each port uses a partition state machine to detect and prevent this condition. When a port suffers from
continuous 64 times of collision events, then it goes to Partition State. The partitioned port will be not released
until a packet without collision be transmitted( more than 512 bit times for AX88872) or reset the repeater.
3.5 Operation of the Built-In Switch
In general, the basic operation of the switch is very simple. The switch receives incoming packets from one of its ports,
searches in the Look-Up Table for the Destination MAC Address and then forwards the packet to the destination ports,
if appropriate. If the destination MAC address is not found in the Look-Up Table, the switch treats the incoming packet
as a broadcast packet and forwards it to all ports except itself. Basically the switch automatically learns the port number
of attached network devices by examining the Source MAC Address of all incoming packets. The device is updated the
table with the Source MAC Address if the Source MAC Address does not exist the table.
3.5.1 Packet Filtering and Forwarding Process
During the receiving process, the switch will monitor the length of the received packet. Legal Ethernet packets should
have a length of no less 64 bytes and nor more than 1528 bytes. The switch discards any packet with illegal length.
After a packet is received, its Source MAC Address and Destination MAC Address are received. The Source MAC
Address is used to update the Look-Up Table and the Destination MAC Address is used to determine the destination port
of the packet. Once a MAC Address has been learned, and the packet is buffered, it must be forwarded, That is, the packet
forwarding mechanism for the switch is handled automatically based on the destination MAC Address.
Under the following conditions, received packets are filtered:
¨
The switch will check all received packets for errors, e.g., FCS error, runt packet, long packet, etc.
¨
Any packet handing to its own source port will be filtered. That is, its destination port is its source port.
¨
The incoming packet will be discarded if the switch’s buffer memory is full.
The switch supports three forwarding modes: Store-and-Forward, Fragment-Free and Auto.
¨
Store-and-Forward Mode: An entry packet is received, checked and stored in the buffer memory before it
is forwarded. That is, each forwarded packet is correct.
¨
Fragment-Free Mode: It is a simple improvement on Cut-Through method. The switch will forward a
packet whose packet length is more than 64 bytes. All runt packets will be filtered in Fragment-Free
mode.
¨
Auto Mode: In Auto mode, the switch select dynamically its optimized forwarding mode based on the
current network quality of each port.
3.5.2 MAC Address Learning and Aging Process
The switch can learn up to 8K unique MAC addresses with a hashing algorithm. Addresses are stored in the Look-Up
Table located in external SSRAM, then each packet updates the table.
The table lookup engine provides the switching information required routing the data packets. The address table is set up
through auto address learning dynamically. After the switch receives a packet, the Source MAC Address and Destination
MAC Address are received. The Source Address retrieved from the received packet is automatically stored in a SA
buffer. The switch will check for error and perform a SA search. The switch will update the Look-Up Table with the
Source MAC Address if there is no error.
The Look-Up Table is cleared on power-on, or hardware reset. When the aging option is enabled, the dynamically
Learned SA will be cleared if it is not refreshed in less than configured time (2 or 5 min).
3.5.3 Flow Control Process
The switch can operate at two different modes: half-duplex and full-duplex. Each port can be configured to have flow
control enabled or not. The switch supports 802.3X for full-duplex operation and uses back pressure for half-duplex.
In full-duplex mode, the switch will receive and transmit the packet in accordance to 802.3X. The transmission channel
and the receiving channel operate independently. If the occupancy of the buffer memory is above the FlowControlActive
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相關代理商/技術參數(shù) |
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| AX88873P | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE Dual Speed 8-Port Repeater |
| AX88875AP | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE 5-Port Dual Speed Bripeater Controller |
| AX-9.84375MAGV-T | 功能描述:晶體 9.84375MHz 30ppm 8pF -40C to 85C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
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