
ASIX ELECTRONICS CORPORATION
10
CONFIDENTIAL
AX88872P Swipeater Controller PRELIMINARY
When RMII mode, the signal is stand for speed indicator. Active for
10Mbps speed is selected depending on power on configuration.
Carrier Sense :
Asynchronous signal SCRS0 is asserted by the PHY
when receive medium is non-idle.
When RMII mode, the signal is stand for CRS_DV (Carrier
Sense/Receive Data Valid ). CRS_DV is asserted asynchronously on
detection of carrier. CRS_DV is asserted by the PHY when receive
medium is non-idle. Loss of carrier shall result in the desertion of
CRS_DV synchronous to the cycle of REF_CLK, which presents the
first DI-bit of a nibble on to RXD0[1:0].
Receive Data Valid :
SRXDV0 is driven by the PHY synchronously
with respect to SRXCLK0. Asserted high when valid data is present on
SRXD0[3:0].
Receive Clock :
SRXCLK0 is a continuous clock that provides the
timing reference for the transfer of the SRXDV0 and SRXD0[3:0]
signals from the PHY to the MII port of the repeater.
Receive Data :
SRXD0[3:0] is driven by the PHY synchronously with
respect to RXCLK.
When RMII mode, SRXD0[1:0] shall transition synchronously to
REF_CLK SRXD0[1:0] shall be “00” to indicate idle when CRS_DV is
disserted. Value other than “00” are reserved for out-of-band signaling
shall be ignored by MAC Upon assertion of CRS_DV, PHY shall ensure
that RXD[1:0] = “00” until proper receive decoding takes place
SCRS0
or
SCRS_DV
I
96
SRXDV0
I
98
SRXCLK0
I
104
SRXD0[3:0]
I
114,113,
111,110
2.2.2 Switch Port 1
Signal Name
STXEN1
Type
O
Pin No.
60
Description
Transmit Enable :
Please references section 2.2.1 SWITCH PORT0
description.
Transmit Data :
Please references section 2.2.1 SWITCH PORT0
description.
Transmit Clock :
Please references section 2.2.1 SWITCH PORT0
description.
Duplex Select :
Please references section 2.2.1 SWITCH PORT0
description.
Collision :
Please references section 2.2.1 SWITCH PORT0
description.
Carrier Sense :
Please references section 2.2.1 SWITCH PORT0
description.
STXD1[3:0]
O
64,63,62,61
STXCLK1
I
65
SDUPLEX1
I
66
SCOL_SP1
I
76
SCRS1
Or
SCRS_DV1
SRXDV1
I
75
I
77
Receive Data Valid :
Please references section 2.2.1 SWITCH PORT0
description.
Receive Clock :
Please references section 2.2.1 SWITCH PORT0
description.
Receive Data :
Please references section 2.2.1 SWITCH PORT0
description.
SRXCLK1
I
78
SRXD1[3:0]
I
82,81,80,79