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參數(shù)資料
| 型號： | AX88796BLF |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | IC,MC14411P |
| 中文描述： | 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應(yīng)快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 51/82頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AX88796BLF |
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ASIX ELECTRONICS CORPORATION
51
AX88796BLF / AX88796BLI
5.1.71 Flow Control Register (FCR)
Offset 1AH (Read/Write)
Field
Name
Description
(Default = 07h)
7
FLWC
Flow-control
0: Flow-control disable (Default)
1: Flow-control enable
6
BPEN
Back Pressure in half-duplex flow-control (AX88796B will ignore this bit when running at
full-duplex mode)
0: Back Pressure disable (Default)
1: Back Pressure enable
5:0
HWPC
High Water free Page Count. Default value is 7 (7 * 256 = 1792 bytes).
5.1.72 MAC Configure Register (MCR)
Offset 1BH (Read/Write)
Field
Name
Description
7
DUPX
MAC duplex mode setting
When read, this bit is indicates the real duplex setting in MAC operation.
0: half-duplex
1: full-duplex
When write, this duplex setting was wire or with TCR bit-7. Each one goes high then
configures MAC as full-duplex mode. AX88796B will ignore this bit and TCR bit-7 when
using internal PHY.
6
BPLE
Back-pressure leakage enable when continuous of collision N times.
N number is reference register 17H of Back-pressure Jam Limit count.
0: Allow flow-control leakage to avoid HUB port going partition state due to too many of
collision (Default)
1: No flow-control leakage
5
BBTC
Back-To-Back Transmission Control:
0: Disable (Default)
1: Enable Back-To-Back Transmission, Host can continue set TXP without check transmit
completed
Host can ignore Number of Collisions Register (NCR)
4
MPSEL
Media Select by Program
0: internal PHY is selected (Default)
1: external MII PHY is selected.
3
VLANE VLAN enable
0: No supported VLAN frame tagged (Default)
1: Only accept Tag frames. AX88796 will reject packet if Tag x8100 and VID not match
whit setting by host. Null VID (VID = 0) is acceptable.
2
CPTEFF Capture effect.
0: always write low (Default)
1: for MAC test only. Force first collision of back off is 2 slot-time and second collision of
back off is 0 slot time. Others as normal.
1
SPMAC Super MAC.
0: always write low (Default)
1: for MAC test only. Back-off only 0 ~ 3 slot-time
0
ZEROBF Zero Back Off Time.
0: always write low (Default)
1: for MAC test only. Back Off Time always zeros.
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PDF描述 |
|---|---|
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| AX88872P | 10/100BASE Dual Speed “Swipeater” Controller |
| AX9902MS | 2N and 2P-Channel Enhancement Mode Power MOSFET |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88796BLI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High-Performance Non-PCI Single-Chip 8/16 bit 10/100M Fast Ethernet Controller |
| AX88796C | 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller |
| AX88796CLF | 制造商:ASIX Electronics Corporation 功能描述: |
| AX88796L | 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
| AX88796LF | 制造商:ASIX 功能描述:10/100 MAC |
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