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參數(shù)資料
| 型號： | AX88796BLF |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | IC,MC14411P |
| 中文描述： | 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應(yīng)快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 37/82頁 |
| 文件大小： | 519K |
| 代理商： | AX88796BLF |
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ASIX ELECTRONICS CORPORATION
37
AX88796BLF / AX88796BLI
5.1.8 Number Of Collisions Register (NCR)
Page0 Offset 05H (Read)
Field
Name
Description (Default = 00h)
7:4
-
Always zero
3:0
NCR
If no collisions are experienced during a transmission attempt, the COL bit of the TSR will
not be set and the contents of NCR will be zero. If there are excessive collisions, the ABT bit
in the TSR will be set and the contents of NCR will be zero. The NCR is cleared after the
TXP bit in the CR is set.
5.1.9 Transmit Byte Count Register (TBCR1)
Page0 Offset 06H (Write)
Field
Name
Description
7:0
TBCR1
Transmit Byte Count Register.
5.1.10 Current Page Register (CPR)
Page0 Offset 06H (Read)
Field
Name
Description (Default = 4Dh)
7:0
CPR
The Buffer Management Logic as a backup register for reception uses this register
internally. CURR contains the address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive errors. This register is initialized
to the same value as PSTART and should not be written to again unless the controller is
Reset.
5.1.11 Interrupt Status Register (ISR)
Page0 Offset 07H (Read/Write)
Field
Name
Description (Default = 80h)
7
RST
Reset Status:
Set when AX88796B enters reset state (or a wake-up event) and cleared when a start
command is issued to the CR. Writing to this bit is no effect.
6
RDC
Remote DMA Complete
Set when remote DMA operation has been completed. Write this bit to high then reset it.
5
CNT
Counter Overflow
Set when MSB of one or more of the Tally Counters has been set. Write this bit to high
then reset its.
4
OVW
OVERWRITE: Set when receive buffer ring storage resources have been exhausted.
Write this bit to high then reset it.
3
TXE
Transmit Error
Set when packet transmitted with one or more of the following errors
Excessive collisions, Transmit over size and late collision.
Write this bit to high then reset it.
2
RXE
Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
Missed Packet
Write this bit to high then reset it.
1
PTX
Packet Transmitted
Indicates packet transmitted with no error
Write this bit to high then reset it.
0
PRX
Packet Received
Indicates packet received with no error.
Write this bit to high then reset it.
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PDF描述 |
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| AX88796BLI | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller |
| AX88872P | 10/100BASE Dual Speed “Swipeater” Controller |
| AX9902MS | 2N and 2P-Channel Enhancement Mode Power MOSFET |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88796BLI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High-Performance Non-PCI Single-Chip 8/16 bit 10/100M Fast Ethernet Controller |
| AX88796C | 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller |
| AX88796CLF | 制造商:ASIX Electronics Corporation 功能描述: |
| AX88796L | 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
| AX88796LF | 制造商:ASIX 功能描述:10/100 MAC |
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