參數(shù)資料
型號： AX88796BLF
廠商： ASIX Electronics Corporation
英文描述： IC,MC14411P
中文描述： 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應快速以太網(wǎng)控制器
文件頁數(shù)： 27/82頁
文件大?。?/td> 519K
代理商： AX88796BLF
ASIX ELECTRONICS CORPORATION
27
AX88796BLF / AX88796BLI
4.4.2 Half-Duplex Flow Control
Whenever the receive buffer becomes full crosses a certain threshold level, The MAC starts sending a Jam signal,
which will result in a collision. After sensing the collision, the remote station will back off its transmit ion.
AX88796B only generate this collision-based of back-pressure when it receives a new frame, in order to avoid any
late collisions.
A programmable of “Back-pressure Jam Limit count” (Offset 17h) is used for avoid HUB port partition due to many
continues of collisions. AX88796B will reset the “Back-pressure Jam Limit count” when either a transmitted or
received frame without collision. A back-pressure leakage allow when senses continue of collisions count up to
“Back-pressure Jam Limit count”, it will be no jamming one of receive frame even receive buffer is full.
4.5 Big- and Little-endian Support
AX88796B supports “Big-“ or “Little-endian” processor. To support big-endian processors, the hardware designer
must explicitly invert the layout of the byte lanes. In addition, for a 16-bit interface, the big-endian register must be
set correctly following the table below.
Additionally, please refer to Big-endian register (offset 1Eh), for additional information on status indication on big-
or little-endian modes.
MODE OFOPERATION AX88796B DATA PINS
SD[15:8]
SD[7:0]
Mode 0 Big-endian register (offset 1Eh) not equal to 0x0000h
Even access
Byte3
Byte2
Odd access
Byte1
Byte0
Mode 0 Little-endian register (offset 1Eh) equal to 0x0000h (default)
Even access
Byte1
Byte0
Odd access
Byte3
Byte2
DESCRIPTION
This mode can be used by 32-bit processors
operating with an external 16-bit bus.
This mode can also be used by native 16-bit
processors.
Tab - 11 Byte Lane Mapping
AX88796B’s 16-bit Data Port (DP) read/write like a FIFO not rely on address pin. The “Even access” means the
first of access Data Port (DP) behind of remote read/write Command Register (CR). The second time access Data
Port (DP) is “Odd access” and then next is “Even access”, and so on.
Host can read bit-7 in “Device Status Register” (Offset 17h) to know the current of big- or little-endian types. The
default is Little-endian mode.
4.6 General Purpose Timer (GP Timer)
The programmable General Purpose Timer can be used to generate periodic host interrupts and the resolution of this
timer is 100us.
The GP timer is a 16-bit of register. GPT1 (CR page3 offset 0Fh) and GPT0 (CR page3 offset 0Eh) to compost this
16-bit of General Purpose Timer. This GP timer field of default value is FFFFh. Once set the General Purpose
Timer Enable (CR page3 Offset 0Dh) the GPT counts down until it reaches 0000h then update the a new pre-load
value into GPT, and continues counting.
The GPT interrupt has no status indicate in Interrupt Status Register (CR page0 offset 07h). The interrupt event will
keep active until host driver read Interrupt Status Register (CR page0 offset 07h) then clear GPT interrupt event.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX88796BLI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High-Performance Non-PCI Single-Chip 8/16 bit 10/100M Fast Ethernet Controller
AX88796C 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller
AX88796CLF 制造商:ASIX Electronics Corporation 功能描述:
AX88796L 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller
AX88796LF 制造商:ASIX 功能描述:10/100 MAC
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