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參數(shù)資料
| 型號： | AX88796BLF |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | IC,MC14411P |
| 中文描述： | 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應(yīng)快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 15/82頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AX88796BLF |
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ASIX ELECTRONICS CORPORATION
15
AX88796BLF / AX88796BLI
4.2 Buffer Management Operation
There are four buffer memory access types used in AX88796B.
1. Packet Reception (Write data to memory from MAC)
2. Packet Transmission (Read data from memory to MAC)
3. Filling Packets to Transmit Buffer (Host fill data to memory)
4. Removing Packets from the Receive Buffer Ring (Host read data from memory)
The type 1 and 2 operations act as Local DMA. Type 1 does Local DMA write operation and type 2 does Local
DMA read operation. The type 3 and 4 operations act as Remote DMA. Type 3 does Remote DMA write operation
and type 4 does Remote DMA read operation.
4.2.1 Packet Reception
The Local DMA receives channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length 256
byte (128 word) buffers for storage of received packets. The location of the Receive Buffer Ring is programmed in
two registers, a Page Start and a Page Stop Register. Ethernet packets consist of minimum packet size (64 bytes) to
maximum packet size (1522 bytes), the 256 byte buffer length provides a good compromise between short packets
and longer packets to most efficiently use memory. In addition these buffers provide memory resources for storage
of back-to-back packets in loaded networks. Buffer Management Logic in the AX88796B controls the assignment
of buffers for storing packets. The Buffer Management Logic provides three basic functions: linking receive buffers
for long packets, recovery of buffers when a packet is rejected, and recalculation of buffer pages that have been read
by the host.
At initialization, a portion of the 16k byte (or 8k word) address space is reserved for the receiver buffer ring. Two
eight bit registers, the Page Start Address Register (PSTART) and the Page Stop Address Register (PSTOP) define
the physical boundaries of where the buffers reside. The AX88796B treats the list of buffers as a logical ring;
whenever the DMA address reaches the Page Stop Address, the DMA is reset to the Page Start Address.
Buffer #1
Buffer #2
Buffer #3
…
…
…
…
Buffer #n
Physical Memory Map
Logic Receive Buffer Ring
Fig - 4 Receive Buffer Ring
4000h
8000h
Page Start
Page Stop
1
2
3
4
…
n-2
n-1
n
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX88796BLI | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller |
| AX88872P | 10/100BASE Dual Speed “Swipeater” Controller |
| AX9902MS | 2N and 2P-Channel Enhancement Mode Power MOSFET |
| AX9902MSA | 2N and 2P-Channel Enhancement Mode Power MOSFET |
| AXC-051 | ACTIVE FILTER FOR RIPPLE ATTENUATION 5A |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88796BLI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High-Performance Non-PCI Single-Chip 8/16 bit 10/100M Fast Ethernet Controller |
| AX88796C | 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller |
| AX88796CLF | 制造商:ASIX Electronics Corporation 功能描述: |
| AX88796L | 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
| AX88796LF | 制造商:ASIX 功能描述:10/100 MAC |
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