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參數(shù)資料
| 型號： | AU1500PCI_REV1 |
| 英文描述： | AMD Alchemy? Solutions Au1500? PCI Bus Software Support? |
| 中文描述： | 采用AMD Alchemy？解決方案Au1500？ PCI總線的軟件支持？ |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 128K |
| 代理商： | AU1500PCI_REV1 |
Application Note
9
PCI Bus Software Support for the Au1500
Rev. 1.3
August 2002
3.
Au1 physical address to PCI address, and
4.
PCI address to Au1 physical address
The bus address translation routines are necessary since a MIPS virtual address is not [necessarily]
equivalent to a PCI physical address. More specifically, the pci_mwbase and pci_mbar registers
permit mapping a window of Au1500 memory anywhere in PCI memory space. These bus address
translation routines know how to compute, for a given memory location, a PCI address from an Au1
address, and vice versa. In particular, device drivers for PCI devices should use these bus address
translation routines when handling PCI memory addresses, particularly for DMA pointers/buffers.
For example, with the simple host bridge configuration above, the bus address translation routines
merely manipulate the three most significant bits of the address corresponding to the MIPS KSEG0/
KSEG1 designations. In more complicated schemes, the bus address translation routines must include
the pci_mwbase and/or pci_mbar value in the address calculations.
In determining the Au1500 memory window size and location, the following items should be taken
into consideration:
1.
PCI accesses into Au1500 memory must occur to memory that is pre-fetchable.
2.
The Au1 MIPS vector table may be exposed in PCI space, so it may be possible to damage
the vector table.
3.
The Au1500 memory window is located in PCI space via pci_mbar. This register is not visi-
ble to the PCI auto-configuration routine.
PCI-initiated memory accesses to Au1500 memory must be to pre-fetchable memory. When a PCI-
initiated memory access occurs to Au1500 memory, up to 8 words are transferred. As a result, it is not
possible to access the integrated peripherals or other memory locations (such as FIFOs, registers, etc.)
that have side-effects. In most instances, only the Au1500 SDRAM should be accessed from PCI.
Depending upon how the Au1500 memory window is configured, the Au1 core MIPS vector table in
RAM (virtual address 0x80000000, physical address 0x00000000) may be exposed in the PCI space.
Depending upon the application and/or the development status of the associated software, this may
not be desirable. If the Au1 core vector table must be protected, then the pci_mwbase register must be
changed, along with the bus address translation routines, to avoid exposing the MIPS vector table in
PCI space.
During the PCI bus auto-configuration, PCI device MBARs are programmed with address ranges that
do not conflict with other PCI devices. However, the Au1500 itself is not visible during a PCI bus
auto-configuration, so the Au1500 pci_mbar register is programmed independent of the standard PCI
auto-configuration code. See “Auto-Configuration Considerations” on page 11 for more information.
5.3.3
Application-specific Values
The registers
pci_b2bmask_cch, pci_b2bbase0_venid, pci_b2bbase1_id, pci_b2bbase1_id,
pci_mwmask_dev, pci_id, pci_classrev
all contain bitfields that correlate to values in the Au1500
PCI controller configuration space header. The values that are appropriate for the PCI configuration
space header are determined by the application. Consult “Appendix D: Class Codes” of the PCI 2.2
specification, as well as the PCI Special Interest Group, PCISIG, for appropriate values.
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