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Application Note
3
PCI Bus Software Support for the Au1500
Rev. 1.3
August 2002
1. Introduction
The Au1500 System-On-a-Chip, SOC[1], features an integrated 33/66MHz PCI 2.2 compliant bus for
connecting to a variety of external peripherals. This document describes software techniques for
supporting the Au1500’s integrated PCI bus.
This document focuses on the software support and considerations that are needed for an Au1500
integrated PCI controller configured as a host bridge.
For information pertaining to the Au1500 configured as a PCI satellite, see “Satellite Mode” on
page 17.
This document assumes the reader is familiar with the PCI Local Bus Specification version 2.2 [2].
2. MIPS32
Architecture Memory Map
In the MIPS architecture, all addresses (instruction fetches, data loads and data stores) are virtual
addresses [3]. As a result, address translation is always performed on program instruction fetches and
data accesses. The type of address translation depends upon the upper bits of the program address.
The MIPS architecture defines the KUSEG, KSEG0 and KSEG1 regions according to these upper
bits of the program’s virtual address. The program’s 32-bit memory space is thus divided:
Figure 1: MIPS 32-bit Memory Map
The KUSEG region extends from 0x00000000 to 0x7FFFFFFF, a 2GB space which uses translation
look-a-side buffers, TLBs, to determine the corresponding physical address. The KUSEG region is
accessible while the CPU is in either user mode or kernel mode.
The KSEG0 region extends from 0x80000000 to 0x9FFFFFFF, a 512MB space which has a direct
correlation to a physical address. In addition, the KSEG0 region is inherently cacheable; meaning that
both instruction and data caching is occuring for references to this area. The KSEG0 region is only
accessible while the CPU is in kernel mode.
Reserved/KSEG2
KSEG1
KSEG0
KUSEG
Reserved/KSEG3
0x00000000
0x80000000
0xA0000000
0xC0000000
0xE0000000