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參數(shù)資料
| 型號(hào)： | AU1500PCI_REV1 |
| 英文描述： | AMD Alchemy? Solutions Au1500? PCI Bus Software Support? |
| 中文描述： | 采用AMD Alchemy？解決方案Au1500？ PCI總線的軟件支持？ |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 128K |
| 代理商： | AU1500PCI_REV1 |
4
Application Note
Rev. 1.3
August 2002
PCI Bus Software Support for the Au1500
The KSEG1 region extends from 0xA0000000 to 0xBFFFFFFF, a 512MB space which also has a
direct correlation to a physical address. However, the KSEG1 region is inherently non-cacheable;
meaning that any instruction or data reference will bypass the cache and directly access physical
memory. The KSEG1 region is only accessible while the CPU is in kernel mode.
For the KSEG0 and KSEG1 regions, the corresponding physical address is bits 28:0 of the virtual
address with address bits 31:29 zero. That is, KSEG0 and KSEG1 map directly onto the first 512MB
of physical memory. For example, KSEG0 address 0x80000000 and KSEG1 address 0xA0000000
both map directly onto physical address 0x00000000. The KSEG0 and KSEG1 regions provide two
views of physical memory; one cacheable and one non-cacheable.
The address translation mechanism of the MIPS architecture always presents a physical address to the
memory controllers (and other address decode logic).
3. Au1500 36-Bit Physical Addresses
From the information/memory map in “MIPS 32-bit Memory Map” on page 3, it is apparent that
there is no room to locate a 32-bit PCI address space directly within the MIPS 32-bit memory map!
Fortunately, the MIPS32 architecture specifies a 36-bit physical address space to accomodate large
address spaces, such as the PCI bus. The Au1500 takes advantage of the 36-bit physical address and
locates the PCI address space as such:
Since 36-bit physical addresses are not directly visible to the processor (i.e. through the KSEG0 or
KSEG1 regions), the PCI space must be mapped into the system using a TLB and then accessed using
virtual address pointers (a 32-bit pointer which is translated by a TLB into a 36-bit physical address).
The address translation steps are depicted in “Au1500 PCI Address Translation” on page 5.
Table 1.
Au1500 PCI Address Space Mapping
36-Bit Physical Address
PCI Function
0x4 XXXXXXXX
PCI Memory Space
0x5 XXXXXXXX
PCI I/O Space
0x6 XXXXXXXX
PCI Configuration Space
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