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參數(shù)資料
| 型號： | AU1500PCI_REV1 |
| 英文描述： | AMD Alchemy? Solutions Au1500? PCI Bus Software Support? |
| 中文描述： | 采用AMD Alchemy？解決方案Au1500？ PCI總線的軟件支持？ |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 128K |
| 代理商： | AU1500PCI_REV1 |
14
Application Note
Rev. 1.3
August 2002
PCI Bus Software Support for the Au1500
Note:
NOTE: The least significant bit of the device number field is masked off during address
translation with a 4KB PageMask (a 4KB PageMask utilizes bits [31:12] of the virtual
address). As a result, least significant bit of the device number field (bit 11) must be included
in the computation of the register offset from the virtual base of the PCI configuration space.
The CCA encoding for the TLB entry must be the value 2 for non-cached accesses.
After a PCI configuration space access, examine the pci_config[ERD,ET,EF,EP] bits for access
errors.
See the sample PCI bus scan code which demonstrates this technique.
6.4.2
Configuration Space Access Technique #2
Technique #2 is quite similar to technique #1, but it simplifies the management of the PCI
configuration space. If the hardware design allows, more specifically all device IDSELs are
connected to one of PCI_AD[24:11] and no Type 1 configuration cycles are needed, then a single
fixed (i.e. wired) TLB entry can be established to cover the useful PCI configuration space. Thus the
PCI configuration space is not continually mapped and unmapped during run-time.
A TLB entry (e.g. TLB index 0) must be allocated for the specific purpose of PCI configuration
cycles. The MIPS CP0 register Wired (i.e. CP0 register 6) must be adjusted accordingly to prevent
random TLB updates from over-writing the entry allocated to the PCI configuration space. The TLB
PageMask is set to 16MB and utilizes both EntryLo0 and EntryLo1 to map a continguous 32MB of
PCI configuration space.
A TLB-translated address range (KUSEG, KSEG2 or KSEG3) must be reserved for the purpose of
providing a 32MB window into PCI configuration space. This is not a general purpose solution, but
may suit many embedded hardware and software designs. The PCI configuration headers for devices
with IDSEL connected to one of PCI_AD[24:11] are then directly visible in this KUSEG/KSEG2/
KSEG3 address range.
The CCA encoding for the TLB entry must be the value 2 for non-cached accesses.
After a PCI configuration space access, examine the pci_config[ERD,ET,EF,EP] bits for access
errors.
See the sample PCI bus scan code which demonstrates this technique.
6.4.3
Configuration Space Access Technique #3
Technique #3, on the other hand, permits device drivers in operating systems that do support a
separate virtual address space for device drivers (e.g. Windows CE) to dynamically map/unmap PCI
configuration address space. The driver utilizes the established mapping/unmapping routines and the
resulting virtual pointers to access PCI configuration space, and therefore the need to dedicate a fixed
TLB entry and reserve a KUSEG address is un-necessary.
In all techniques, the CCA encoding for the TLB entry must be the value 2 for non-cached accesses.
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