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參數(shù)資料
| 型號(hào)： | AU1500PCI_REV1 |
| 英文描述： | AMD Alchemy? Solutions Au1500? PCI Bus Software Support? |
| 中文描述： | 采用AMD Alchemy？解決方案Au1500？ PCI總線的軟件支持？ |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 128K |
| 代理商： | AU1500PCI_REV1 |
Application Note
15
PCI Bus Software Support for the Au1500
Rev. 1.3
August 2002
7. PCI Memory Space
The Au1 core is able to generate non-cache-able accesses, cache-able accesses and fast back-to-back
accesses to PCI memory. All PCI accesses first travel through the Au1500 TLB to yield a 36-bit
physical address and a CCA encoding to determine cache-ability. The Au1500 PCI controller also
features different types of windows into PCI space to improve performance.
7.1
Non-cache-able Accesses
Non-cache-able accesses are designated by the TLB producing the 36-bit physical address
0x4 xxxxxxxx with a CCA encoding of 2 or 7. On a read to non-cache-able PCI memory space, the
Au1 core stalls waiting for data, and on a write, the data flows through the write-buffer, stalling only
if the write-buffer is full.
A CCA encoding of 2 prevents gathering in the write buffer, which in turns causes single-beat
accesses to PCI memory. CCA encoding 7 permits gathering in the write buffer, which in turns allows
for burst transfers on the PCI bus. See Au1500 data book “2.3 Write Buffer” for more information.
In general, non-cache-able PCI memory space accesses occur when referencing PCI device registers
and/or memory and tend to be the most frequent type of PCI memory space access.
7.2
Cache-able Accesses
Generally speaking, PCI memory space on the Au1500 is non-cache-able. However, the Au1500 PCI
controller features the pci_cmem register which creates a cache-able window into PCI memory space.
To utilize this feature, the pci_cmem must be enabled and the TLB must produce a physical address
that hits in pci_cmem address range and a CCA encoding of 4.
The pci_cmem[CM_BASE] value is inherently prepended with 0x0 to compare against a 36-bit
physical address (the Au1 core cache tags are for a 32-bit physical address). If the physical address
hits in pci_cmem, then a cache-able PCI memory access takes place.
Note:
NOTE: It is NOT possible to use the TLB (with CCA 4) by itself to acheive cache-able PCI
memory space accesses. The Au1 core cache tags are 32-bit physical address tags, and so a
36-bit physical address, like PCI memory space 0x4 xxxxxxxx, is inherently non-cache-able.
The cache-able PCI memory window can be located anywhere, and in particular, within the first
512MB of memory; the MIPS KSEG0 region. However, to use the cache-able PCI memory window
in KSEG0, the Config[K0] field, the CCA encoding for the KSEG0 region, must be set to 4. Do note,
though, that changing KSEG0 to CCA 4 may not be suitable for all/most applications since it may
introduce more processor stalls (since the critical word is no longer accessed first).
A very important consideration in determining to use the cache-able PCI memory window is that
cache-able PCI memory window is
NOT
coherent with the PCI memory space. As such, the cache-
able PCI memory window may not be suitable for all applications.
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