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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ATMEGA324P-B15MZ
寤犲晢锛� Atmel
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 42/70闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 8BIT 32KB FLASH 44VQFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 4,000
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 16MHz
閫i€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 32KB锛�16K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 1K x 8
RAM 瀹归噺锛� 2K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 44-VFQFN 瑁搁湶鐒婄洡(p谩n)
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū(ch膿ng)锛� ATMEGA324P-B15MZ-ND
31
7674F鈥揂VR鈥�09/09
ATmega164P/324P/644P
7.2.2
Clock Startup Sequence
Any clock source needs a sufficient V
CC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient V
CC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. 鈥淥n-chip Debug System鈥� on page 45
describes the start conditions for the internal reset. The delay (t
TOUT) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
selectable delays are shown in Table 7-2. The frequency of the Watchdog Oscillator is voltage
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The
delay will not monitor the actual voltage and it will be required to select a delay longer than the
Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be
used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay
can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is
not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-
ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal
reset active for a given number of clock cycles. The reset is then released and the device will
start to execute. The recommended oscillator start-up time is dependent on the clock type, and
varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when
the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is
assumed to be at a sufficient level and only the start-up time is included.
7.2.3
Clock Source Connections
The pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which
can be configured for use as an On-chip Oscillator, as shown in Figure 7-2 on page 32. Either a
quartz crystal or a ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. For ceramic resonators, the capacitor values given by
the manufacturer should be used.
Table 7-2.
Number of Watchdog Oscillator Cycles
Typ Time-out (V
CC = 5.0V)
Typ Time-out (V
CC = 3.0V)
Number of Cycles
0 ms
0
4.1 ms
4.3 ms
512
65 ms
69 ms
8K (8,192)
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ATMEGA324PB-AN 鍔熻兘鎻忚堪:IC MCU 8BIT 32KB FLASH 44TQFP 鍒堕€犲晢:microchip technology 绯诲垪:AVR? ATmega 鍖呰:鎵樼洡(p谩n) 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 鏍稿績铏曠悊鍣�:AVR 鏍稿績灏哄:8-浣� 閫熷害:20MHz 閫f帴鎬�:I2C锛孲PI锛孶ART/USART 澶栬ō(sh猫):娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT I/O 鏁�(sh霉):39 绋嬪簭瀛樺劜(ch菙)瀹归噺:32KB锛�16K x 16锛� 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨�:闁冨瓨 EEPROM 瀹归噺:1K x 8 RAM 瀹归噺:2K x 8 闆诲 - 闆绘簮锛圴cc/Vdd锛�:1.8 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 8x10b 鎸暕鍣ㄩ(l猫i)鍨�:鍏�(n猫i)閮� 宸ヤ綔婧害:-40掳C ~ 105掳C锛圱A锛� 灏佽/澶栨:44-TQFP 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:44-TQFP 妯�(bi膩o)婧�(zh菙n)鍖呰:160
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